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Quality Electronic Design (ISQED), 2010 11th International Symposium on

Date 22-24 March 2010

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Displaying Results 1 - 25 of 146
  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • [Spine]

    Publication Year: 2010, Page(s): 1
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  • [Title page]

    Publication Year: 2010, Page(s): i
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  • [Copyright notice]

    Publication Year: 2010
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  • Welcome to ISQED 2010

    Publication Year: 2010, Page(s): iii
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  • ISQED quality Award recipient (IQ-Award 2010)

    Publication Year: 2010, Page(s): iv
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  • ISQED 2010 best papers

    Publication Year: 2010
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  • SQED 2010 Organizing Committee

    Publication Year: 2010, Page(s):vi - xi
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  • ISQED 2010 fellow Award recipient

    Publication Year: 2010, Page(s): xii
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  • ISQED 2010 - table of contents

    Publication Year: 2010, Page(s):xiii - xix
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  • Call for papers

    Publication Year: 2010, Page(s): 1
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  • Preliminary call for papers

    Publication Year: 2010, Page(s): 1
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  • Notes [blank page]

    Publication Year: 2010, Page(s): 1
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  • Limits of bias based assist methods in nano-scale 6T SRAM

    Publication Year: 2010, Page(s):1 - 8
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (397 KB) | HTML iconHTML

    Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. Large scale 6T SRAM arrays beyond 65 nm will increasingly rely on assist methods to overcome the functional limitations imposed by increased variation, reduced overdrive and the inherent read stability/write margin trade off. Factors such ... View full abstract»

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  • Variability resilient low-power 7T-SRAM design for nano-scaled technologies

    Publication Year: 2010, Page(s):9 - 14
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (593 KB) | HTML iconHTML

    High variability in nano-scaled technologies can easily disturb the stability of a carefully designed standard 6T-SRAM cell, causing access failures during a read/write operation. We propose a 7T-SRAM cell to increase the read/write stability under large variations. The proposed design uses a low overhead read/write assist circuitry to increase the noise immunity. Use of an additional transistor a... View full abstract»

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  • Robust importance sampling for efficient SRAM yield analysis

    Publication Year: 2010, Page(s):15 - 21
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8684 KB) | HTML iconHTML

    Monte Carlo simulations have been widely adopted for analyzing circuit properties, such as SRAM yield, under strong influence of process variations. Enormous calculation time is required in such a simulation due to the low defect probabilities. In this paper, we propose a robust shift-vector determination for mean-shift importance sampling, by which efficiency and stability of the Monte Carlo simu... View full abstract»

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  • An accurate modeling method utilizing application-specific statistical information and its application to SRAM yield estimation

    Publication Year: 2010, Page(s):22 - 28
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB) | HTML iconHTML

    In this paper, we propose a new model construction method utilizing application specific physical information and present its application to SRAM yield calculation. The physical information is extracted as statistical distributions from past simulation results automatically. Experimental results show our method achieves 700x speed up over non modeling method and more than 10x speed up over the con... View full abstract»

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  • Adaptive power gating for function units in a microprocessor

    Publication Year: 2010, Page(s):29 - 37
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    This paper describes adaptive fine-grain control to power gate function units based on temperature dependent break-even time (BET). An analytical model to express the temperature dependent BET is introduced and the accuracy of the model was examined. Results demonstrated that the model well represents the exponential decrease in BET with the temperature. Meanwhile, it was found that the accuracy g... View full abstract»

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  • A dual-level adaptive supply voltage system for variation resilience

    Publication Year: 2010, Page(s):38 - 43
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (235 KB) | HTML iconHTML

    VLSI circuits of 45 nm technology and beyond are increasingly affected by process variations as well as aging effects. Overcoming the variations inevitably requires additional power expense which in turn aggravates the power and heat problem. Adaptive supply voltage (ASV) is an arguably power-efficient approach for variation resilience since it attempts to allocate power resources only to where th... View full abstract»

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  • A low power charge-redistribution ADC with reduced capacitor array

    Publication Year: 2010, Page(s):44 - 48
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (733 KB) | HTML iconHTML

    This paper presents a novel design of low power charge redistribution successive approximation analog to digital converter (CR-SAR ADC). During its conversion, the voltage swing of the capacitor array is reduced to half of the voltage reference without decreasing the ADC dynamic range. The reduced voltage swing results in a significant reduction of ADC power consumption. Also, the proposed design ... View full abstract»

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  • Leakage current analysis for intra-chip wireless interconnects

    Publication Year: 2010, Page(s):49 - 53
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6302 KB) | HTML iconHTML

    A simulation-based feasibility study of an intra-chip wireless interconnect system is presented. The wireless interconnect system is modelled in a 250 nm standard complementary metal-oxide semiconductor (CMOS) technology operating at typical conditions. A finite element method (FEM) based 3-D full-wave solver is used to perform the electromagnetic field analysis. In the field analysis, the effects... View full abstract»

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  • Toward effective utilization of timing exceptions in design optimization

    Publication Year: 2010, Page(s):54 - 61
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9951 KB) | HTML iconHTML

    Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-functional critical paths. Ideally, timing exceptions should always be helpful for quality of results (QOR) metrics such as area or number of timing violations, and for design turnaround time (TAT) metrics such as tool runtime and nu... View full abstract»

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  • Useful clock skew optimization under a multi-corner multi-mode design framework

    Publication Year: 2010, Page(s):62 - 68
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3748 KB) | HTML iconHTML

    As VLSI technology scales into sub-65 nm realm, the complexity of timing optimization is drastically increased by the consideration of power and variations. Even though designers make great efforts during physical design, they are often faced with still heavy timing violations in deep post-routing stages. For the entire design convergence and timing closure, especially under current multi-corner m... View full abstract»

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  • Clock buffer polarity assignment considering the effect of delay variations

    Publication Year: 2010, Page(s):69 - 74
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (218 KB) | HTML iconHTML

    This work addresses the problem of minimizing power/ground noise with an important design parameter, which is the delay variations on the clock tree. Without considering the effect of delay variations on the polarity assignment, the resulting statistical clock skew may lead to a high probability of skew violation, which causes a low yield of design. Given distributions on the delay of each type of... View full abstract»

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  • Linear time calculation of state-dependent power distribution network capacitance

    Publication Year: 2010, Page(s):75 - 80
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7311 KB) | HTML iconHTML

    A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance... View full abstract»

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