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Solid-State Circuits, IEEE Journal of

Issue 4 • Date Apr 1993

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Displaying Results 1 - 18 of 18
  • Low-power 1/2 frequency dividers using 0.1-μm CMOS circuits built with ultrathin SIMOX substrates

    Page(s): 510 - 512
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    Four types of frequency dividers were fabricated on SIMOX/SOI (separation by implanted oxygen/silicon on insulator) substrates. A novel circuit among these four circuits showed the highest operation frequency of 1.2 GHz under 1-V supply voltage, with gate lengths of 0.15 and 0.1 μm. Power consumption was no more than 50 and 62 μW for both 0.15- and 0.1-μm gate designs, respectively View full abstract»

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  • An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS

    Page(s): 447 - 454
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    A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Hardware cost is minimized by sharing resistor strings, bias circuitry and clock generation circuitry over the array. Digital error correction is employed to ease comparator accuracy requirements. Techniques are employed to minimize the effect of mismatches across the array. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode operational-amplifier topology is used. An experimental chip was implemented in 1-μm CMOS and 8-b resolution at a sample rate of 85 megasamples per second (MS/s) was obtained. Signal-to-noise plus distortion (S/(N+D)) was 41 dB for an input sinusoid of 40 MHz View full abstract»

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  • Design techniques for high-throughput BiCMOS self-timed SRAMs

    Page(s): 484 - 489
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    Design techniques for a high-throughput BiCMOS self-timed SRAM are described. A new BiCMOS read circuit using a pipelined read architecture and a BiCMOS complementary clocked driver (BCCD) are proposed to reduce the operating cycle time. A 8192×9-b dual-port self-timed SRAM designed using the proposed techniques achieved a clock cycle time of 3.0 ns, that is, a 333-MHz operating frequency, by SPICE simulation on model parameters for 0.8-μm BiCMOS technology. A high-speed built-in self-test (BIST) circuit was studied and designed for the 3.0-ns cycle SRAM. It is confirmed that the BIST circuit allows the 3.0-ns cycle SRAM to test at its maximum operating frequency View full abstract»

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  • A 500-megabyte/s data-rate 4.5 M DRAM

    Page(s): 490 - 498
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    A 512-kb×9 DRAM with a 500-Mbyte/s data transfer rate was developed. This high data rate was achieved by designing a DRAM core with a very high internal column bandwidth, and coupling this core with a block-oriented, small-swing, synchronous interface that uses skew-canceling clocks. The DRAM has a 1-kbyte×2-line sense-amp cache and is assembled in a 32-pin vertical surface-mount-type plastic package. The measurement results clearly verified the 500-Mbyte/s data rate View full abstract»

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  • A low-power 12-b analog-to-digital converter with on-chip precision trimming

    Page(s): 455 - 461
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    The design and performance of a 12-b charge redistribution analog-to-digital converter (ADC) is described. The architecture is chosen to minimize power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a 1-μm CMOS process. It converts at a 200-kHz rate with a power dissipation of 10 mW View full abstract»

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  • Low-power on-chip supply voltage conversion scheme for ultrahigh-density DRAMs

    Page(s): 504 - 509
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    In order to achieve 3.3-V 1-Gb DRAM and beyond, a new on-chip supply voltage conversion scheme that converts 3.3-V external supply voltage, Vext, to lowered 1.5-V internal supply voltage, Vent, without any power loss within the voltage converter is proposed. This scheme connects two identical DRAM circuits in series between Vixt and Vss. By operation of two DRAM circuits with the same clock timing, the voltage between two DRAMs, Vint, is automatically fixed to 1/2Vext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2Vext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAMs. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty View full abstract»

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  • Variable VCC design techniques for battery-operated DRAMs

    Page(s): 499 - 503
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    Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting VCC level; (2) compensation of DC generators, VBB and VPP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable VCC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation View full abstract»

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  • A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture

    Page(s): 523 - 527
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    Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM View full abstract»

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  • A CCD/CMOS-based imager with integrated focal plane signal processing

    Page(s): 431 - 437
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    Using a CCD/CMOS technology, a fully parallel 4×4 focal plane processor, which performs image acquisition, smoothing, and segmentation, has been fabricated and characterized. In this chip, image brightness is converted into signal charge using charge-coupled-device (CCD) imaging techniques. The Gaussian smoothing operation is approximated by the repeated application of a simple nearest-neighbor binomial convolution mask, realizing the first known use of a true two-dimensional charge division and transfer process. The design allows full control of the spatial extent of the smoothing operation, and incorporates segmentation circuits with global variable threshold control at each pixel location to preserve edges in the image. The processed image is read out using a standard CCD clocking scheme View full abstract»

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  • Low-voltage ULSI design

    Page(s): 408 - 413
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    An overall view on low-voltage device and circuit design is presented, beginning with a discussion of the low-voltage limit. Low-voltage device design is then described. Low-voltage CMOS and BiCMOS logic circuits are discussed. Circuit techniques for the low-voltage DRAMs and SRAMs are presented. The low-voltage analog devices and circuits are considered. The future direction of the low-voltage and low-power ULSIs is discussed by comparing the switching energy of electronic devices and brain cells View full abstract»

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  • Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits

    Page(s): 420 - 430
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    An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed View full abstract»

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  • A Si bipolar 1.4-GHz time space switch LSI for B-ISDN

    Page(s): 518 - 522
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    A 155-MB/s 32×32 Si bipolar switch LSI designed for wide application in the broadband ISDN was implemented. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies were developed for the LSI: (1) an active pull-down circuit with an embedded bias circuit in each gate, and (2) a modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area were reduced to 60% and 70%, respectively, of what is expected when conventional emitter-coupled logic (ECL) technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system View full abstract»

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  • A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

    Page(s): 478 - 483
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    A 1-Mb (256 K×4) CMOS SRAM with 6-ns access time is described. The SRAM, having a cell size of 3.8 μm×7.2 μm and a die size of 6.09 mm×12.94 mm, is fabricated by using 0.5-μm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new NMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle View full abstract»

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  • A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescaler using a divide-by-2/3 synchronous counter

    Page(s): 513 - 517
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    An extremely low-power CMOS/SIMOX divide-by-128/129 dual-modulus prescaler that operates at up to 1 GHz and dissipates 0.9 mW at a supply voltage of 1 V is presented. The prescaler is capable of 2-GHz performance with dissipation of 7.2 mW at 2 V. This superior performance is primarily achieved by using an advanced ultrathin-film CMOS/SIMOX process technology combined with a circuit configuration that uses a divide-by-2/3 synchronous counter. Using these same technologies, a single-chip CMOS phase-locked-loop (PLL) LSI that uses the developed prescaler was fabricated. It can operate at up to 2 GHz while dissipating only 8.4 mW at a supply voltage of 2 V. Even at a lower supply voltage of 1.2 V, 1-GHz operation can be obtained with a corresponding power consumption of 1.4 mW. These results indicate that the high-speed and very-low-power features of CMOS/SIMOX technology could have an important impact on the development of future personal communication systems View full abstract»

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  • Sub-1-V swing internal bus architecture for future low-power ULSIs

    Page(s): 414 - 419
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    A bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of bus driver circuits and bus receiver circuits to reduce the bus signal swing while maintaining a low standby current. The bus driver circuit has a source offset configuration, achieved by the use of low-VT MOSFETs and an internal supply voltage corresponding to the reduced signal swing. The bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new bus driver and receiver enables the bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3-μm processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization View full abstract»

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  • A 10-b 300-MHz interpolated-parallel A/D converter

    Page(s): 438 - 446
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    A monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz is described. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor Vbe matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within ±0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of -59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0-mm×4.2-mm chip integrating 36 K elements, which consumes 4.0 W using a 1.0-μm-rule, 25-GHz ft, double-polysilicon self-aligned bipolar technology View full abstract»

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  • An interpolative bandpass converter on a 1.2-μm BiCMOS analog/digital array

    Page(s): 471 - 477
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    The architecture and performance of an interpolative bandpass A/D converter (ADC) and digital quadrature demodulator dedicated for digital narrowband transmission systems, like the cellular radio mobile receiver, are presented. A prototype version has been implemented on a 1.2-μm/7-GHz BiCMOS analog/digital array. A bandpass signal centered at 6.5 MHz with 200-kHz bandwidth is demodulated and converted with a 55-dB signal-to-noise ratio giving 9-b performance View full abstract»

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  • A 20-MHz sixth-order BiCMOS parasitic-insensitive continuous-time filter and second-order equalizer optimized for disk-drive read channels

    Page(s): 462 - 470
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    A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. The 20-MHz sixth-order Bessel filter and second-order equalizer operate from 5 V and generate only 0.24% (-52 dB) of total harmonic distortion when processing 2-Vpp differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36 Mb/s and is built in a 1.5-μm, 4-GHz BiCMOS technology View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan