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Micro, IEEE

Issue 2 • Date March-April 2010

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Displaying Results 1 - 15 of 15
  • [Front cover]

    Publication Year: 2010 , Page(s): c1
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  • Contents

    Publication Year: 2010 , Page(s): c2
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  • Masthead

    Publication Year: 2010 , Page(s): 1
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  • Bleeding-Edge Mass Market Standards [Micro Economics]

    Publication Year: 2010 , Page(s): 2 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB) |  | HTML iconHTML  

    To have a large impact, bleeding-edge mass market standards must do two things: diffuse widely and provide new functionality. Curiously, however, although these standards are often built from advanced technologies, they cannot deploy on a wide scale without building upon other widely deployed routines or less-advanced processes. A new standard's ultimate impact is often uncertain at the time of deployment for numerous reasons. Technical constraints or simple lack of imagination, for example, might prevent participants from designing a perfect standard at the outset. View full abstract»

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  • Guest Editors' Introduction: Hot Chips 21

    Publication Year: 2010 , Page(s): 5 - 6
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  • Power7: IBM's Next-Generation Server Processor

    Publication Year: 2010 , Page(s): 7 - 15
    Cited by:  Papers (69)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB) |  | HTML iconHTML  

    The Power7 is IBM's first eight-core processor, with each core capable of four-way simultaneous-multithreading operation. Its key architectural features include an advanced memory hierarchy with three levels of on-chip cache; embedded-DRAM devices used in the highest level of the cache; and a new memory interface. This balanced multicore design scales from 1 to 32 sockets in commercial and scientific environments. View full abstract»

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  • Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor

    Publication Year: 2010 , Page(s): 16 - 29
    Cited by:  Papers (34)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (713 KB) |  | HTML iconHTML  

    The 12-core AMD Opteron processor, code-named "Magny Cours," combines advances in silicon, packaging, interconnect, cache coherence protocol, and server architecture to increase the compute density of high-volume commodity 2P/4P blade servers while operating within the same power envelope as earlier-generation AMD Opteron processors. A key enabling feature, the probe filter, reduces both the bandwidth overhead of traditional broadcast-based coherence and memory latency. View full abstract»

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  • Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing

    Publication Year: 2010 , Page(s): 30 - 40
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (654 KB) |  | HTML iconHTML  

    The Sparc64 VIIIfx eight-core processor, developed for use in petascale computing systems, runs at speeds of up to 2 GHz and achieves a peak performance of 128 gigaflops while consuming as little as 58 watts of power. Sparc64 VIIIfx realizes a six-fold improvement in performance per watt over previous generation Sparc64 processors. View full abstract»

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  • Ubiquitous Parallel Computing from Berkeley, Illinois, and Stanford

    Publication Year: 2010 , Page(s): 41 - 55
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (570 KB) |  | HTML iconHTML  

    The ParLab at Berkeley, UPCRC-Illinois, and the Pervasive Parallel Laboratory at Stanford are studying how to make parallel programming succeed given industry's recent shift to multicore computing. All three centers assume that future microprocessors will have hundreds of cores and are working on applications, programming environments, and architectures that will meet this challenge. This article briefly surveys the similarities and difference in their research. View full abstract»

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  • The GPU Computing Era

    Publication Year: 2010 , Page(s): 56 - 69
    Cited by:  Papers (125)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (694 KB) |  | HTML iconHTML  

    GPU computing is at a tipping point, becoming more widely used in demanding consumer applications and high-performance computing. This article describes the rapid evolution of GPU architectures-from graphics processors to massively parallel many-core multiprocessors, recent developments in GPU computing architectures, and how the enthusiastic adoption of CPU+GPU coprocessing is accelerating parallel applications. View full abstract»

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  • Instruction Set Innovations for the Convey HC-1 Computer

    Publication Year: 2010 , Page(s): 70 - 79
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (705 KB) |  | HTML iconHTML  

    The Convey HC-1 is a heterogeneous computing system based on an industry-standard Intel processor and a proprietary coprocessor that share virtual memory and an instruction stream, creating a hybrid-core computing system. The coprocessor architecture supports user-defined, dynamically loadable instruction sets. Managing the decoding, dispatch, and execution of completely user-defined instructions requires an innovative approach to system design and operation. View full abstract»

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  • Silicon MEMS Oscillators for High-Speed Digital Systems

    Publication Year: 2010 , Page(s): 80 - 89
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1074 KB) |  | HTML iconHTML  

    Recent advances in microelectromechanical system (MEMS) manufacturing and circuit design techniques have propelled MEMS-based silicon oscillators into the mainstream of electronic components. This article discusses the reasons for this trend, which include size, reliability, mass manufacturability, and performance advantages in various digital applications, such as processors and parallel and serial interfaces. View full abstract»

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  • Designing for Discovery [review of "Search Patterns" Design for Discovery" (Morville, P. and Callender, J.; 2010)]

    Publication Year: 2010 , Page(s): 90 - 92
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  • [Advertisement - Back cover]

    Publication Year: 2010 , Page(s): c3
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  • [Advertisement - Back cover]

    Publication Year: 2010 , Page(s): c4
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Aims & Scope

High-quality technical articles from designers, systems integrators, and users discussing the design, performance, or application of microcomputer and microprocessor systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center