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Solid-State Circuits, IEEE Journal of

Issue 3 • Date Mar 1993

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Displaying Results 1 - 25 of 28
  • An image processing IC for backprojection and spatial histogramming in a pipelined array

    Page(s): 210 - 221
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    The first VLSI digital signal processor that performs both high-precision image backprojection and spatial histogram calculations at raster-scan rates as high as 30 MHz is described. Realized in 1 μm CMOS technology, this 13.3 mm×13.3 mm chip is designed to handle images as large as 1024×1024 12 b pixels. Loadable coefficients and a unified architecture allow this IC to be used with a variety of computed-tomography scanners for image reconstructions, including fan- and parallel-beam reconstruction. This chip also computes the forward Radon transform, which is a spatial histogram, permitting it to be used for iterative reconstruction algorithms. The bit lengths in the fixed-point architecture assure 12 b reconstruction accuracy View full abstract»

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  • A fourth-order bandpass sigma-delta modulator

    Page(s): 282 - 291
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    The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta (ΣΔ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio View full abstract»

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  • A single-chip video ghost canceller

    Page(s): 379 - 383
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    A 450 K-transistor video ghost canceller chip, which implements a flexibly configurable IIR and FIR filter, is described. A very compact digital filter tap operating at a pixel rate of 14.32 MHz (4×F sc) allows 180 programmable taps to be implemented in a die area of 56.25 mm2 in a 1 μm TLM CMOS process. The device operates with 3.3- or 5-V power supplies View full abstract»

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  • Statistical integrated circuit design

    Page(s): 193 - 202
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (896 KB)  

    Several statistical design methods that have been developed to minimize the effects of IC manufacturing process disturbances on circuit performance are reviewed. It is shown that statistical design problems can be expressed as optimization problems in which either the objective function or the constraint functions depend on expectations of random variables. The effectiveness of the most recent such method, the boundary integral method is illustrated with several circuit design examples View full abstract»

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  • Synthesizing embedded speed-optimized architectures

    Page(s): 242 - 252
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    A global optimization approach to high-level synthesis of speed-optimized embedded VLSI architectures is presented. Two mathematical integer programming (IP) models are presented. The first simultaneously selects types of functional units, performs scheduling tasks, and allocates hardware. The second additionally minimizes latency and optimally selects a clock period simultaneously with scheduling and allocation. By exploiting the problem structure, using polyhedral theory, the size of the search space of both IP models is decreased, thus improving the IP solution efficiency. This approach breaks new ground by simultaneously scheduling and allocating with complex and asynchronous interface constraints, to minimize both the average execution time and the area, automatically minimizing latency by optimally selecting the clock period and types of functional units (including chained operations), and synthesizing globally optimal architectures of embedded VLSI chips in practical CPU execution times View full abstract»

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  • Design and characterization of analog VLSI neural network modules

    Page(s): 301 - 313
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    A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 μm double-polysilicon CMOS technologies are presented to demonstrate the testing procedure View full abstract»

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  • Circuits to reduce distortion in the diode-bridge track-and-hold

    Page(s): 384 - 387
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    Circuits for reducing distortion in the diode-bridge track-and-hold are described. Adding circuits with current and voltage feedback can reduce distortion caused by the droop and nonlinear junction capacitance of a transistor. A high-speed complementary bipolar process technology is incorporated in the circuit design for its flexibility. SPICE II simulation demonstrates that the circuits reduce distortion in the diode-bridge track-and-hold by 10 to 20 dB View full abstract»

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  • A 200 MHz CMOS broad-band switching chip

    Page(s): 269 - 275
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    The architecture of a 32-channel, 200 MHz Batcher-Banyan fabric chip for broadband ATM packet switching is described, as well as the design methods required to develop a 380 K-transistor CMOS device that operates at these speeds under worst-case conditions. This device routes packets from 32 sources to any 32 destinations, is completely reconfigured each packet period, maintains priorities, supports contention resolution, and is a building block for larger switches View full abstract»

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  • A VLSI chip set for a large-scale parallel inference machine: PIM/m

    Page(s): 344 - 351
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    The authors present three VLSI chips-a processor (PU) chip, a cache memory (CU) chip, and a network control (NU) chip-for a large-scale parallel inference machine. The PU chip has been designed to be adapted to logic programming languages such as PROLOG. The CU chip implements a hardware support called `trial buffer' which is suitable for the execution of the PROLOG-like languages. The NU chip makes it possible to connect 256 processing elements in a mesh network. The parallel inference machine (PIM/m) runs a PROLOG-like network-based operating system called PIMOS as well as many applications and has a peak performance of 128 mega logical inferences per second (MLIPS). The PU chip containing 384000 transistors is fabricated in a 0.8 μm double-metal CMOS technology. The CU chip and the NU chip contain 610000 and 329000 transistors, respectively. They are fabricated in a 1.0 μm double-metal CMOS technology. A cell-based design method is used to reduce the layout design time View full abstract»

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  • Design techniques for a compatible single and dual supply analog cell library

    Page(s): 392 - 396
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    Techniques for building an analog-cell library that can operate with a single or dual power supply without user intervention are presented. The cells have been designed to be easily incorporated into a mixed-signal VLSI system. These techniques lead to fewer cells in a given library because a single cell can operate on both a single and dual supply. Conventional approaches would typically result in twice the number of cells in order to accommodate single and dual power supplies. To demonstrate the feasibility of the single and/or dual supply concept, the cell library has been used to construct both a parallel and a serial output 10-b plus sign A/D converter. Detailed circuitry is given for the substrate voltage sensor, a TTL-compatible input stage, a general-purpose analog multiplexer (MUX), a master bias circuit, an adjustable precision bandgap reference, and an autozero circuit View full abstract»

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  • A GaAs four-quadrant analog multiplier circuit

    Page(s): 388 - 391
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    A design for a four-quadrant analog multiplier is presented using GaAs MESFETs. The fabricated circuit has a -3 dB bandwidth of 410 MHz with 50-Ω/6.5-pF output loading, nonlinearity of less than 1%, and static power dissipation of 86.1 mW with Vdd=3 V and Vss=-2 V. Simulations indicate the circuit will operate at frequencies over 2.0 GHz with on-chip loads of 0.15 pF View full abstract»

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  • A SONET/SDH overhead terminator for STS-3, STS-3C, and STM-1

    Page(s): 276 - 281
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    A single-chip synchronous optical network/synchronous digital hierarchy (SONET/SDH) overhead terminator has been designed for use in STS-3, STS-3C, and STM-1 applications. The chip has been fabricated in a 1 μm CMOS process and contains 220000 transistors. The features supported by the chip include overhead extraction, overhead insertion, alarm detection, alarm generation, performance monitoring, pointer tracking, pointer generation, payload retiming, and payload realignment. The architecture of the IC and several of the chip's more interesting features are described View full abstract»

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  • 10 Gb/s silicon bipolar 8:1 multiplexer and 1:8 demultiplexer

    Page(s): 339 - 343
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    High-speed multiplexer and demultiplexer circuits are key components in high-speed optical communication systems such as SONET. As optical communication link speeds increase, faster electronic interface circuitry is required. The use of multiplexer circuits allows most of the electronic circuitry to operate on parallel data at a lower speed, reducing the speed requirements of much of the system. A retimed 8:1 multiplexer and a 1:8 demultiplexer which operate at 10 Gb/s are described. These circuits were fabricated in high-speed silicon bipolar process. Design optimization techniques were used to achieve maximum performance. The retimed multiplexer and the demultiplexer dissipate 3.8 and 4.3 W, respectively View full abstract»

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  • CDMA mobile station modem ASIC

    Page(s): 253 - 260
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    An implementation of a complete modulator/demodulator (modem) for use in portable and mobile cellular telephones implementing code-division multiple-access (CDMA) digital technology is described. Key features are high circuit density and complexity, a short design cycle, flexibility, testability, and low power consumption. A universal microprocessor interface allows for efficient control, data transfer, and testability of the ASIC. The chip is fabricated in double-metal 0.8 μm CMOS technology and implements a mixture of custom and synthesized design approaches. The power consumption is less than 350 mW at 5 V View full abstract»

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  • PROXIMA: PROlog eXecutIon MAchine

    Page(s): 362 - 370
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    The design and the technological aspects involved in the integration of a high-performance Prolog machine on silicon are described. Many Prolog machines have been implemented by using a large number of boards. Consequently they are expensive, cumbersome, and not yet achievable by industrial standards. There have been many attempts in the US, Japan, and Europe to integrate Prolog engines in silicon, in order to increase performance. The described processor, PROXIMA (PROlog eXecutIon MAchine), is a VLSI Prolog engine suitable to be added onto a commercial workstation. The PROXIMA chip set has been integrated in silicon using a double-metal 0.8 μm n-well SGS-Thomson proprietary CMOS technology View full abstract»

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  • A 180 MHz 0.8 μm BiCMOS modular memory family of DRAM and multiport SRAM

    Page(s): 222 - 232
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    A family of modular memories with a built-in self-test interface designed using a synchronous self-timed architecture is described. This approach is ideally suited to modular memories embedded within synchronous systems due to its simple boundary specification, excellent speed/power performance, and ease of modelling. The basic port design is self-contained and extensible to any number of ports sharing access to a common-core cell array. The same design has been used to implement modular one-, two-, and four-part SRAMs and a one-port DRAM based on a four-transistor (4-T) cell. The latter provides a 45% core cell density improvement over the one-port SRAM. Nominal access and cycle times of 5.5 ns for 64 kb blocks have been shown for a 0.8 μm BiCMOS process with no memory process enhancements. System operation at 100 MHz has been demonstrated on a broadband time-switch chip containing 96 kb of two-port SRAM View full abstract»

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  • Reduced implementation of D-type DET flip-flops

    Page(s): 400 - 402
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    One of the main disadvantages of using D-type double-edge triggered flip-flops (DET-FFs) in VLSI system design is the number of transistors required. Two new DET-FF circuits (one static, the other dynamic) are proposed in which the number of transistors is reduced to a number similar to that for classic single-edge triggered flip-flops (SET-FFs). Both new circuits not only behave correctly when operated at high frequency but also offer a good level of immunity to metastability problems (static) and race problems (dynamic), as well as presenting a simple straightforward layout. These considerations offer wider practical and economic applications for the use of DET-FFs in VLSI system design View full abstract»

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  • Hierarchical yield estimation of large analog integrated circuits

    Page(s): 203 - 209
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    A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive View full abstract»

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  • Sizing of cell-level analog circuits using constrained optimization techniques

    Page(s): 233 - 241
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    A CAD tool that accurately sizes analog circuits in short-channel CMOS processes using SPICE-quality device models and constrained optimization techniques is presented. All knowledge about device behavior is embedded within an encapsulated device evaluator which simplifies the description of the analog circuit that must be provided by an expert designer, and makes that description independent of the specific device type and technology. The use of constrained optimization allows the KCL and KVL constraints that determine the DC operating point of a circuit to be formulated and solved for simultaneously with the performance constraints. In addition, the constrained optimization formulation of the analog design problem makes it easy for the user to study trade-offs in the circuit design space by varying the performance constraints. Simulation results demonstrate the tool's ability to accurately synthesize high-performance two-stage CMOS operational amplifiers in 2 μm and 1.2 μm CMOS processes View full abstract»

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  • A 60 MBd, 480 Mb/s, 256 QAM decision-feedback equalizer in 1.2 μm CMOS

    Page(s): 330 - 338
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    Using a combination of architecture optimization techniques and unconventional circuit designs, a 60 MHz decision-feedback equalizer (DFE) chip is presented for high-bit-rate digital modem applications. The equalizer can accommodate quaternary phase-shift keying (QPSK), and 16, 64, and 256 quadrature amplitude modulation (QAM) and achieves a peak throughput rate of 480 MB/s. The chip contains four complex-valued programmable filter taps and incorporates coefficient updating circuitry for implementing the LMS adaptive algorithm with user-selectable adaptation step sizes. Cut-set retiming architecture techniques were used so that the chips could be cascaded to implement longer equalizer lengths without any speed degradation, and a circuit design technique called adaptively biased pseudo-NMOS logic (APNL) was adopted to reduce on-chip critical-path delays. The fully parallel chip architecture achieves a computational throughput of 1.44 billion operations per second (GOPS) View full abstract»

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  • A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unit

    Page(s): 375 - 378
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    A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 μm BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder View full abstract»

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  • A 10 b 50 MHz pipelined CMOS A/D converter with S/H

    Page(s): 292 - 300
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    A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology View full abstract»

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  • A 320 MFLOPS CMOS floating-point processing unit for superscalar processors

    Page(s): 352 - 361
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    A CMOS pipelined floating-point processing unit (FPU) for superscalar processors is described. It is fabricated using a 0.5 μm CMOS triple-metal-layer technology on a 61 mm2 die. The FPU has two execution modes to meet precise scientific computations and real-time applications. It can start two FPU operations in each cycle, and this achieves a peak performance of 160 MFLOPS double or single precision with an 80 MHz clock. Furthermore, the original computation mode, twin single-precision computation, double the peak performance and delivers 320 MFLOPS single precision. Its full bypass reduces the latency of operations, including load and store, and achieves an effective throughput even in nonvectorizable computations. An out-of-order completion is provided by using a new exception prediction method and a pipeline stall technique View full abstract»

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  • Diode-biased AC-coupled ECL-to-CMOS interface circuit

    Page(s): 397 - 399
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    A full CMOS emitter-coupled logic (ECL)-to-CMOS voltage level converter has been developed. A diode-biased AC-coupled circuit is used to convert digital signals from ECL to CMOS voltage levels for use in digital data transmission. This technique makes the receiver insensitive to variations in input signal noise and offset voltage with no substantial penalties in conversion delay. The circuit can be used to retrofit all-CMOS systems to a bipolar ECL environment and to benefit from the reduction of chip-to-chip delays using small-signal transmission-line networks View full abstract»

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  • CMOS continuous-time current-mode filters for high-frequency applications

    Page(s): 323 - 329
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    Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 μm n-well CMOS process achieved a -3 dB cutoff frequency (f 0) of 42 MHz; f0 was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 μA. Using a single 5 V power supply with a nominal reference current of 100 μA, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm2/pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 μm n-well CMOS process to verify the implementation of finite transmission zeros View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan