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Power Electronics, IEEE Transactions on

Issue 3 • Date March 2010

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Displaying Results 1 - 25 of 30
  • [Front cover]

    Page(s): C1
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    Freely Available from IEEE
  • IEEE Transactions on Power Electronics publication information

    Page(s): C2
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    Freely Available from IEEE
  • Table of contents

    Page(s): 537 - 538
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  • An Integrated EMI Choke for Differential-Mode and Common-Mode Noise Suppression

    Page(s): 539 - 544
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB) |  | HTML iconHTML  

    This letter presents a novel integration approach for the electromagnetic interference choke. A low-permeability differential-mode (DM) choke is placed within the open window of the common-mode (CM) choke. Both chokes share the same winding structure. With the proposed approach, the footprint of inductors is greatly reduced, and high-DM inductance can be achieved. First, small-signal measurement is carried out to demonstrate the design concept and the symmetry of the proposed structure. Then large-signal experimental results verify the attenuation characteristics, as well as the thermal performance. View full abstract»

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  • Three-Phase Multilevel PWM Rectifiers Based on Conventional Bidirectional Converters

    Page(s): 545 - 549
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (391 KB) |  | HTML iconHTML  

    Almost two decades of research on unidirectional three-phase multilevel boost-type pulsewidth modulation (PWM) rectifiers have shown the benefits of employing this technology to comply with power quality standards while assuring high efficiency and low volume and weight. However, the unidirectional topologies directly derived from the conventional three-level bidirectional converters, such as the neutral point clamped (NPC), the flying capacitor and the cascaded H-bridge converters have not been properly analyzed. This letter introduces some of the unidirectional topologies that arise from the inspection of the widespread conventional bidirectional converters. Special emphasis is put in the analysis of the NPC-based three-phase/-level PWM rectifier operating as power factor corrector. View full abstract»

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  • Ripple Current Reduction of a Fuel Cell for a Single-Phase Isolated Converter Using a DC Active Filter With a Center Tap

    Page(s): 550 - 556
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (559 KB) |  | HTML iconHTML  

    A ripple current reduction method is proposed that does not require additional switching devices. A current ripple that has twice the frequency component of the power supply is generated in the dc part when a single-phase pulsewidth-modulated inverter is used for a grid connection. The current ripple causes shortening of the lifetime of electrolytic capacitors, batteries, and fuel cells. The proposed circuit realizes a dc active filter function without increasing the number of switching devices, because the energy buffer capacitor is connected to the center tap of the isolation transformer. In addition, the buffer capacitor voltage is controlled by the common-mode voltage of the inverter. The features of the proposed circuit, control strategy, and experimental results are described, including the result of ripple reduction, to approximately 20% that of the conventional circuit. View full abstract»

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  • Digital Controller for DVS-Enabled DC–DC Converter

    Page(s): 557 - 573
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    A high-frequency digital controller that includes an optimized analog-digital converter (ADC) with a novel formulation of digital error value based on target clock frequency and converter output voltage is presented in this paper. A programmable look-up table-based digital compensator is implemented for fast processing the feedback error. Limitations of a hybrid digital pulsewidth modulator (DPWM) at high frequency are addressed and solved by an edge-triggered logic. Support for process, voltage, and temperature variations is incorporated in the integrated design. Target clock frequency denotes the frequency of the signal which is driven by dynamic voltage scaling (DVS) processor and corresponds to the reference value of the regulated output voltage. This work realizes the classical digital controller design implementation of a target frequency to minimum required regulated voltage for DVS-enabled adaptive DC-DC converter. A synchronous buck converter of 1 MHz switching frequency and the proposed delay-line-based optimized ADC have been fabricated for realizing and verifying the complete digital controller on a field-programmable gate array-based closed-loop prototype. Experimental results are presented, which demonstrate the fast dynamic response achieved for target clock frequency in the range of 6-16 MHz, corresponding to the regulated output voltage range of 1.6-3.2 V. The complete design of digital controller has been implemented in 0.5 ??m CMOS technology using Cadence and Synopsys tools. The active on-chip area of the proposed delay-line ADC, digital compensator, and edge-triggered hybrid DPWM are 0.08, 0.28, and 0.07 mm2 respectively. View full abstract»

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  • LED Driver Circuit with Series-Input-Connected Converter Cells Operating in Continuous Conduction Mode

    Page(s): 574 - 582
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (275 KB) |  | HTML iconHTML  

    This paper introduces an LED driver circuit implemented by series-input-connected converter cells with a common duty cycle control approach operating from a dc voltage bus. With this structure, low-voltage high-frequency ICs and low-profile components can be applied in high-voltage applications. Flexibility is provided for the cells to work under different voltage supply conditions by simply changing the number of series converters. With the converters operating in continuous conduction mode, the common duty cycle control approach enables automatic line voltage sharing and output current copying. The approach results in a control-to-output transfer function of the system close to that of a single converter for ease of feedback loop design. The modular approach also allows continued operation in the presence of open-circuit LED failures. Design considerations and experimental results are presented for a 25-W three-cell system with 9 Luxeon K2 high-brightness LEDs, demonstrating line voltage sharing, output current copying, and LED failure response. View full abstract»

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  • Comparison of Trench Gate IGBT and CIGBT Devices for Increasing the Power Density From High Power Modules

    Page(s): 583 - 591
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1606 KB) |  | HTML iconHTML  

    Recently much research has been focused on increasing the functionality and output power density per unit area in power electronic modules without increasing board space. In high power applications, MOS-controlled devices with trench gates are the most desirable as their reduced V ce(sat) enables increased conduction current density. However, with increased drift region thickness, there is significant increase in conduction loss in trench gate-insulated gate bipolar transistor (T-IGBT) due to low plasma density from inherent p-n-p transistor action. In comparison, a well-designed MOS-controlled thyristor structure such as the trench-clustered insulated gate bipolar transistor (T-CIGBT), can provide low on-state conduction loss with gate voltage turn-on and turn-off. The comparison of 3.3 kV/800 A simulation results presented in this paper shows that the T-CIGBT is a superior candidate over TIGBT to increase the power density from existing high-voltage IGBT module footprints. View full abstract»

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  • A Method of Reducing the Peak-to-Average Ratio of LED Current for Electrolytic Capacitor-Less AC–DC Drivers

    Page(s): 592 - 601
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    This paper proposes a concept of electrolytic capacitor-less light-emitting diode (LED) driver, which converts the commercial ac voltage to a pulsating current with twice the line frequency driving high-brightness LEDs. As no electrolytic capacitor is used, this driver possesses the unique advantage of long lifetime to match with that of LEDs. A method of injecting the third and fifth harmonics into the input current to reduce the peak-to-average ratio of the output current is also proposed. While ensuring that the input power factor is higher than 0.9 to meet regulation standards such as ENERGY STAR, the proposed method allows the peak-to-average ratio of the output current to be reduced to 1.34 theoretically, which is beneficial for the safe operation of the LEDs. As an example, a flyback-based electrolytic capacitor-less LED driver is proposed, and its operation is analyzed. In order to inject the third and fifth harmonics into the input current, the function of the duty cycle in a half-line cycle is derived. It is then simplified to a fitting function, which can be easily implemented with the input voltage sensing. A 25 V, 0.35 A output prototype is built and tested in the laboratory, and the experimental results are presented to verify the effectiveness of the electrolytic capacitor-less LED driver and its control method. View full abstract»

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  • Passive Lossless Snubber for Boost PFC With Minimum Voltage and Current Stress

    Page(s): 602 - 613
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1029 KB) |  | HTML iconHTML  

    A passive lossless snubber for boost power-factor corrector (PFC) is presented. It has a number of advantages over the prior art. First, it does not introduce extra voltage and current stress on the main switch. Second, it provides soft-switching conditions for the main switch over wide input and load range. Third, it limits the turn- on current of the main switch resulting from the reverse recovery current of the output diode. The operating principle of the proposed snubber and procedure of designing the component values are given. A comparative study into the performance characteristics between the prior-art passive lossless snubbers and the proposed snubber will be performed. The performance of the proposed snubber has been evaluated experimentally on a 750-W PFC with universal input. The boost converter is operated in continuous conduction mode and its input current is shaped by using average current-mode control. Experimental results show that soft switching of the main switch is maintained over 88% with an input of 110 V, 60 Hz, and 91.8% an the input of 220 V, 50 Hz, over one line cycle, and from full load to 20% load. The efficiencies of the PFC with unsnubbered hard switching, conventional resistor-capacitor-diode snubber, and proposed snubber will be compared. Results show that the proposed snubber can significantly improve the efficiency over the designed operating range. View full abstract»

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  • A Dual-Mode Single-Inductor Dual-Output Switching Converter With Small Ripple

    Page(s): 614 - 623
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    Single-inductor dual-output (SIDO) switching converters always suffer from large ripple and severe cross-regulation problem, when a large inductor current is switched between two outputs. This paper proposes a novel fly capacitor method for SIDO converters to reduce the output ripple and spike. An adaptive common-mode control is presented to suppress the cross-regulation problem. A duty-ratio-based current estimation method is proposed to detect the load current, and the converter can automatically switch between pulsewidth modulation and pulse-frequency modulation modes. The two outputs of the converter are specified for 1.2 V/400 mA and 1.8 V/200 mA with input voltage ranging from 2.7 to 5 V. The chip has been fabricated on a 0.25-?? m CMOS mixed-signal process. The conversion efficiency is 82% at a total output power of 840 mW, while the output ripple is about 20 mV and spike is less than 40 mV. The maximum overshot voltage during load response is 50 mV. View full abstract»

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  • A 1-MHz, 12-V ZVS Nonisolated Full-Bridge VRM With Gate Energy Recovery

    Page(s): 624 - 636
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1850 KB) |  | HTML iconHTML  

    In this paper, a new self-driven zero-voltage-switching (ZVS) nonisolated full-bridge converter is presented for 12-V input VRM applications. The advantages of the new circuit are: 1) duty cycle extension; 2) ZVS of all the control MOSFETs; 3) lower voltage stress and reduced reverse recovery loss of the synchronous rectifier (SR) MOSFETs; 4) high-drive voltage to reduce R DS( ON) and the conduction loss of the SRs due to gate energy recovery capability; and 5) reduced body-diode conduction and no external drive IC chips with dead time control needed for SRs. Existing multiphase buck controllers and buck drivers can be directly used in the proposed converter. The experimental results verify the principle of operation and significant efficiency improvement. At 12 V input, 1.3 V output voltage, and 1 MHz switching frequency, the proposed converter improves the efficiency, using the buck converter from 80.7% to 83.6% at 50 A, and from 77.9% to 80.5% at 60 A. With two parallel SRs, the efficiency is further improved from 83.6% (single SR) to 84.7% (two SRs) and at 60 A, the efficiency is improved from 80.5% (single SR) to 83.2% (two SRs). View full abstract»

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  • Modeling and Control of Three-Port DC/DC Converter Interface for Satellite Applications

    Page(s): 637 - 649
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1225 KB) |  | HTML iconHTML  

    This paper presents the control strategy and power management for an integrated three-port converter, which interfaces one solar input port, one bidirectional battery port, and an isolated output port. Multimode operations and multiloop designs are vital for such multiport converters. However, control design is difficult for a multiport converter to achieve multifunctional power management because of various cross-coupled control loops. Since there are various modes of operation, it is challenging to define different modes and to further implement autonomous mode transition based on the energy state of the three power ports. A competitive method is used to realize smooth and seamless mode transition. Multiport converter has plenty of interacting control loops due to integrated power trains. It is difficult to design close-loop controls without proper decoupling method. A detailed approach is provided utilizing state-space averaging method to obtain the converter model under different modes of operation, and then a decoupling network is introduced to allow separate controller designs. Simulation and experimental results verify the converter control design and power management during various operational modes. View full abstract»

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  • Design of High-Efficiency Bidirectional DC–DC Converter and High-Precision Efficiency Measurement

    Page(s): 650 - 658
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (685 KB) |  | HTML iconHTML  

    This paper first introduces the design of an ultrahigh efficiency 50-kW bidirectional dc-dc converter at zero-voltage-switching operation, and then, a high-precision efficiency measurement method using a regenerative approach. The ultrahigh efficiency bidirectional dc-dc converter is achieved with 1) the use of CoolMOS as the main switch under zero-voltage soft switching condition; 2) multiple-phase legs for current sharing to reduce the conduction loss; and 3) coupling inductors between each two-phase legs to reduce the core loss. Two identical hardware prototypes were designed, fabricated, and tested for performance evaluation. In order to precisely measure the converter efficiency, the two identical bidirectional dc-dc converters are tested with one as the device under test and the other as the regenerative unit. With the use of ?? 0.5% current shunt and regenerative measurement, the relative efficiency error stays below ??0.025%. Measured efficiency with load from 20% to 100% consistently shows above 97.50%. At the 50 kW full-load condition, the efficiency is 99.05% with ??0.01% efficiency relative error. View full abstract»

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  • A Generic Six-Step Direct PWM (SS-DPWM) Scheme for Current Source Converter

    Page(s): 659 - 666
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1200 KB) |  | HTML iconHTML  

    This paper aims to explore the pulsewidth modulation (PWM) schemes for three-phase current source converter, and a generic six-step direct PWM (SS-DPWM) scheme is proposed. In the SS-DPWM, one line cycle is divided into six 60?? intervals, so called as ??six-step.?? During each interval, only two of the three references, referred to as the Master and Slave references, respectively, compare with the carriers to directly generate the required switching patterns instead of using the transformation from bilogic signals to trilogic ones, as used in the conventional sinusoidal PWM (SPWM). In this paper, the variety of the Slave reference for each interval is identified, and many sets of modulating waveforms are presented for the SS-DPWM, resulting in very flexible and expanded modulations. The mechanism of the SS-DPWM is also presented to develop its modulating characteristics, and it is shown that, comparing with the conventional SPWM, the SS-DPWM has lower switching frequency, higher dc current utilization ratio, and in-phase transfer between the line currents and their references. A prototype has been built in the lab and the validity of the theoretical analysis is verified by the experimental results. View full abstract»

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  • Analysis and Design of Forward Converter With Energy Regenerative Snubber

    Page(s): 667 - 676
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB) |  | HTML iconHTML  

    An energy regenerating snubber for a forward converter is presented. The proposed snubber uses a tertiary transformer winding and beneficially exploits transformers' leakage inductances. The proposed snubber is capable of resetting the transformer, as well as eliminating leakage inductance voltage spike across the power switch. The proposed snubber recycles the recovered energy partially to the load and partially back to the source. This paper presents theoretical analysis, simulation and experimental results. View full abstract»

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  • A Three-Phase High-Frequency Semicontrolled Rectifier for PM WECS

    Page(s): 677 - 685
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB) |  | HTML iconHTML  

    This paper proposes the use of a three-phase high-frequency semicontrolled rectifier for wind energy conversion systems based on permanent magnet generators. The main advantages of the topology are: simplicity, since all active switches are connected to a common point, robustness, as short-circuit through a leg is not possible, and high efficiency due to reduced number of elements. As a disadvantage, higher but acceptable total harmonic distortion of the generator currents results. The complete operation of the converter and theoretical analysis are presented. Additionally, a single-phase pulsewidth modulation inverter is also employed in the grid connection. Experimental results on 5-kW prototype are presented and discussed. View full abstract»

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  • A ZCS Full-Bridge Converter Without Voltage Overstress on the Switches

    Page(s): 686 - 698
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1511 KB) |  | HTML iconHTML  

    A new current-driven soft-switched full-bridge converter is presented in this paper. By connecting a switched-capacitor snubber in parallel with the primary winding of the coupling transformer, all main switches are zero-current-switched (ZCS) and the switches in the snubber are zero-voltage-switched (ZVS). The proposed converter has the following key features. First, the transformer leakage inductance is utilized as a part of the resonant circuit for the soft-switching actions. Second, the snubber capacitor voltage is adaptively controlled: the capacitor is charged to the minimum necessary energy for switching the main switches at zero current, depending on the actual value of the input/load current. Thus, less resonant energy is circulated. Third, there is no extra voltage stress on the switches and the current through the switches is limited to the value of the input current. Consequently, the conduction losses are kept minimum. The cyclical switching operation and control of the converter are described. A tradeoff design of the snubber circuit is given: the requirement of reducing the duration of the resonant intervals for minimizing the duty-cycle loss is superimposed on the requirement of getting ZCS for a very large range of the line voltage and load. A 530-V/15-kV, 5-kW prototype has been built and evaluated. The experimental results confirmed the theoretical predictions. A comparative study on the converter efficiency with and without the proposed snubber circuit is given, showing the superiority of the proposed solution. View full abstract»

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  • Modeling of Cold Cathode Fluorescent Lamps (CCFLs) With Realistic Electrode Profile

    Page(s): 699 - 709
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1574 KB) |  | HTML iconHTML  

    Compared with conventional fluorescent lamps, the cold cathode fluorescent lamps (CCFLs) are more compact in size and have a longer lifetime. Therefore, they are widely used as an illuminating source and background lighting in liquid crystal display panels and notebook computers. However, a suitable CCFL model that can be used by ballast designers is lacking. This paper proposes a simple and user-friendly CCFL model that can help a ballast designer to predict the electrical characteristics of a CCFL under different operating frequencies and dimming conditions. The model is developed based on the energy balance equations governing the discharge process of CCFLs and the prediction of the amplitude and shape of the cathode voltage drop in CCFLs. The simulation results show that the model can accurately predict the lamp's electrical characteristics under both low and high operating frequencies. View full abstract»

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  • An Electromagnetic Interference (EMI) Reduced High-Efficiency Switching Power Amplifier

    Page(s): 710 - 718
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1581 KB) |  | HTML iconHTML  

    The design of a new high-efficiency switching power amplifier with an ultralow-power spread spectrum clock generator (SSCG) is first reported in this paper. An effective low-power frequency modulation method is first proposed to reduce the electromagnetic interference of the pulse width modulation class D power amplifier without degrading its power efficiency. Also, a simple RC voltage feedback circuit is used to reduce the total harmonic distortion (THD). This amplifier proves to be a cost-effective solution for designing high fidelity and high efficiency audio power amplifiers for portable applications. Measurement results show that the power efficiency and THD can reach 90% and 0.05%, respectively. The power dissipation of the SSCG is only 112 ??W. The harmonic peaks of the switching frequency are greatly reduced when the SSCG technique is applied to the amplifier design. The impact of the SSCG on the THD of the class D power amplifier is also first reported in this paper. This switching power amplifier is implemented using a Taiwan Semiconductor Manufacture Company (TSMC) 0.35- ??m CMOS process. View full abstract»

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  • Hybrid Buck–Boost Feedforward and Reduced Average Inductor Current Techniques in Fast Line Transient and High-Efficiency Buck–Boost Converter

    Page(s): 719 - 730
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2343 KB) |  | HTML iconHTML  

    This paper presents a buck-boost converter with high efficiency and small output ripple to extend the battery life of portable devices. Besides, the hybrid buck-boost feedforward (HBBFF) technique is integrated in this converter to achieve fast line response. The new control topology minimizes the switching and conduction losses at the same time even when four switches are used. Therefore, over a wide input voltage range, the proposed buck-boost converter with minimum switching loss like the buck or boost converter can reduce the conduction loss through the use of the reduced average inductor current (RAIC) technique. Moreover, the HBBFF technique minimizes the voltage variation at the output of error amplifier. Consequently, a fast line transient response can be achieved with small dropout voltage at the output. Especially, the converter can offer good line and load regulations to ensure a regulated output voltage without being affected by the decreasing battery voltage. Experimental results show that the output voltage is regulated over a wide battery lifetime, and the output ripple is minimized during mode transition. The peak efficiency is 97% and the transient dropout voltage can be improved substantially. View full abstract»

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  • A System-in-Package (SiP) With Mounted Input Capacitors for Reduced Parasitic Inductances in a Voltage Regulator

    Page(s): 731 - 740
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1093 KB) |  | HTML iconHTML  

    This paper presents a system-in-package (SiP) that mounts an input capacitor for voltage regulators. The SiP has a low power loss of 3.8 W at a switching frequency of 1 MHz, input voltage of 12 V, and output current of 25 A. The parasitic inductance of this SiP is 56% that of the previously reported SiP, which had the input capacitor mounted on the printed circuit board, and this reduction is due to the short current loop from the input capacitor to the MOSFETs. As a result, the power loss can be reduced by 20% for the same spike voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the drain electrode of the high-side MOSFET and the source electrode of the low-side MOSFET to the mounted input capacitor. The authors also propose a way to estimate the parasitic inductance experimentally, not from a current measurement such as with a shunt resistor and a current probe, but from the ringing frequency when the high-side MOSFET is switched and the output capacitance C oss of the MOSFET being on the off state. View full abstract»

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  • A Novel Phase-Interleaving Algorithm for Multiterminal Systems

    Page(s): 741 - 750
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1239 KB) |  | HTML iconHTML  

    This paper introduces a novel phase-interleaving algorithm for asymmetric multiterminal power converters. Using a variable phase interleaving (VI), the first harmonic of the dc-link current and voltage can be thoroughly eliminated even under the situation where the input voltage and current of each converter differ. This means that the cost and size of the dc-link capacitor can be significantly reduced compared to when the standard (symmetric) interleaving algorithm is used. The VI-algorithm does not require any additional hardware and has only slight influence on the control loop of the converters when compared to the standard solution, which simplifies the integration of this algorithm. As a concrete application, the VI-algorithm is integrated into a photovoltaic inverter with three independent input converters. This paper also provides a method for determining the required dc-link capacitance through a worst-case analysis. Furthermore, a performance comparison between edge-aligned fixed interleaving, center-aligned fixed interleaving and VI and is given. View full abstract»

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  • An Integral Battery Charger With Power Factor Correction for Electric Scooter

    Page(s): 751 - 759
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (797 KB) |  | HTML iconHTML  

    This paper presents an integral battery charger for an electric scooter with high voltage batteries and interior-permanent-magnet motor traction drive. The battery charger is derived from the power hardware of the scooter, with the ac motor drive that operates as three-phase boost rectifier with power factor correction capability. The control of the charger is also integrated into the scooter control firmware that is implemented on a fixed-point DSP controller. Current-controlled or voltage-controlled charge modes are actuated according to the requirements of the battery management system, that is embedded into the battery pack. With respect to previous integrated chargers, the ac current is absorbed at unitary power factor with no harmonic distortion. Moreover, no additional filtering is needed since the pulsewidth modulation ripple is minimized by means of phase interleaving. The feasibility of the integral charger with different ac motors (induction motor, surface-mounted phase modulation motor) is also discussed, by means of a general model purposely developed for three-phase ac machines. The effectiveness of the proposed battery charger is experimentally demonstrated on a prototype electric scooter, equipped with two Li-ion battery packs rated 260 V, 20 Ah. View full abstract»

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Aims & Scope

IEEE Transactions on Power Electronics covers fundamental technologies used in the control and conversion of electric power.

Full Aims & Scope