By Topic

Computers, IEEE Transactions on

Issue 5 • Date May 2010

Filter Results

Displaying Results 1 - 15 of 15
  • [Front cover]

    Publication Year: 2010 , Page(s): c1
    Save to Project icon | Request Permissions | PDF file iconPDF (118 KB)  
    Freely Available from IEEE
  • [Inside front cover]

    Publication Year: 2010 , Page(s): c2
    Save to Project icon | Request Permissions | PDF file iconPDF (141 KB)  
    Freely Available from IEEE
  • Guest Editors' Introduction: Special Section on System-Level Design of Reliable Architectures

    Publication Year: 2010 , Page(s): 577 - 578
    Save to Project icon | Request Permissions | PDF file iconPDF (78 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • Formal Reliability Analysis Using Theorem Proving

    Publication Year: 2010 , Page(s): 579 - 592
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (697 KB) |  | HTML iconHTML  

    Reliability analysis has become a tool of fundamental importance to virtually all electrical and computer engineers because of the extensive usage of hardware systems in safety and mission critical domains, such as medicine, military, and transportation. Due to the strong relationship between reliability theory and probabilistic notions, computer simulation techniques have been traditionally used ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions

    Publication Year: 2010 , Page(s): 593 - 607
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (5018 KB) |  | HTML iconHTML  

    The shrinking processor feature size, lower threshold voltage, and increasing clock frequency make modern processors highly vulnerable to transient faults. Architectural Vulnerability Factor (AVF) reflects the possibility that a transient fault eventually causes a visible error in the program output, and it indicates a system's susceptibility to transient faults. Therefore, the awareness of the AV... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Concurrent Structure-Independent Fault Detection Schemes for the Advanced Encryption Standard

    Publication Year: 2010 , Page(s): 608 - 622
    Cited by:  Papers (28)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1796 KB) |  | HTML iconHTML  

    The Advanced Encryption Standard (AES) has been lately accepted as the symmetric cryptography standard for confidential data transmission. However, the natural and malicious injected faults reduce its reliability and may cause confidential information leakage. In this paper, we study concurrent fault detection schemes for reaching a reliable AES architecture. Specifically, we propose low-cost stru... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Microarchitectural Online Testing for Failure Detection in Memory Order Buffers

    Publication Year: 2010 , Page(s): 623 - 637
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3309 KB) |  | HTML iconHTML  

    Technology scaling leads to burn-in phase out and higher postsilicon test complexity, which increases in-the-field failure rate due to both latent defects and actual errors, respectively. As a consequence, current reliability qualification methods will likely be infeasible. Microarchitecture knowledge of application runtime behavior offers a possibility to have low-cost continuous online testing t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • PERFECTORY: A Fault-Tolerant Directory Memory Architecture

    Publication Year: 2010 , Page(s): 638 - 650
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3296 KB) |  | HTML iconHTML  

    The number of CPUs in chip multiprocessors is growing at the Moore's Law rate, due to continued technology advances. However, new technologies pose serious reliability challenges, such as more frequent occurrences of degraded or even nonoperational devices, and they threaten the cost-effectiveness and dependability of future computing systems. This work studies how to protect the on-chip coherence... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors

    Publication Year: 2010 , Page(s): 651 - 665
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3116 KB)  

    As the semiconductor industry continues its relentless push for nano-CMOS technologies, device reliability and occurrence of hard errors have emerged as a dominant concern in multicores. Although regular memory structures are protected against hard errors using error correcting codes or spare rows and columns, many of the structures within the cores are left unprotected. Even if the location of ha... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Interleaving Structure for Guaranteed QoS in Real-Time Broadcasting Systems

    Publication Year: 2010 , Page(s): 666 - 678
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2816 KB) |  | HTML iconHTML  

    Providing high-quality broadcast services for soft real-time applications over wireless networks such as CDMA2000, which have high bit error rates, requires the control of errors that occur during data transmission. Reed-Solomon (RS) forward error correction (FEC) in the medium access control (MAC) layer performs this role in 3G broadcast services. We propose new analytic models for predicting the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improved Design of High-Performance Parallel Decimal Multipliers

    Publication Year: 2010 , Page(s): 679 - 693
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (4984 KB) |  | HTML iconHTML  

    The new generation of high-performance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multipliers. In this paper, we describe the architectures of two parallel decimal multipliers. The parallel generation of partial products is performed using signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand multiples.... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

    Publication Year: 2010 , Page(s): 694 - 706
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2979 KB) |  | HTML iconHTML  

    Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a new redundant-digit representation for floating-point numbers that leads to computation speedup in two ways: (1) Reducing the per-operation latency when multiple floating-point additions are performed before result conversion... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Adaptation of Reputation Management Systems to Dynamic Network Conditions in Ad Hoc Networks

    Publication Year: 2010 , Page(s): 707 - 719
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2908 KB) |  | HTML iconHTML  

    Reputation management systems have been proposed as a cooperation enforcement solution in ad hoc networks. Typically, the functions of reputation management (evaluation, detection, and reaction) are carried out homogeneously across time and space. However, the dynamic nature of ad hoc networks causes node behavior to vary both spatially and temporally due to changes in local and network-wide condi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • TC Information for authors

    Publication Year: 2010 , Page(s): c3
    Save to Project icon | Request Permissions | PDF file iconPDF (141 KB)  
    Freely Available from IEEE
  • [Back cover]

    Publication Year: 2010 , Page(s): c4
    Save to Project icon | Request Permissions | PDF file iconPDF (118 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org