# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 23 of 23

Publication Year: 2010, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2010, Page(s): C2
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• ### A Brief Introduction to Time-to-Digital and Digital-to-Time Converters

Publication Year: 2010, Page(s):153 - 157
Cited by:  Papers (57)  |  Patents (9)
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This paper presents a short review of time-to-digital and digital-to-time converters (TDCs and DTCs, respectively) adopting a time-mode signal-processing perspective. The primary definitions, operating principles, and basic building blocks are presented. The discussion applies to most, if not all, DTCs and TDCs. A series of voltage-controlled delay units are used as the primary building block of t... View full abstract»

• ### Systematic Design Centering of Continuous Time Oversampling Converters

Publication Year: 2010, Page(s):158 - 162
Cited by:  Papers (33)
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We address the practical problem of determining the loop filter component values in a single-loop continuous-time delta sigma modulator. Conventional techniques to design center the converter to achieve a desired noise transfer function are cumbersome and not numerically stable. We present a robust procedure that can be used to determine the loop filter coefficients when real opamps (with finite g... View full abstract»

• ### A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique

Publication Year: 2010, Page(s):163 - 167
Cited by:  Papers (19)
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In this brief, a split-capacitor correlated double sampling (SC-CDS) technique is proposed to improve the performance of CDS. Using the proposed technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined analog-to-digital converter (ADC). A power-efficient class-AB pseudodifferential op-amp and its corresponding integrator-based common-mode stabilizatio... View full abstract»

• ### Bias-and-Input Interchanging Technique for Cyclic/Pipelined ADCs With Opamp Sharing

Publication Year: 2010, Page(s):168 - 172
Cited by:  Papers (12)
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This brief proposes a bias-and-input interchanging (BII) technique for resetting opamp summing nodes to remove the memory effect of residue signals in cyclic/pipelined analog-to-digital converters (ADCs) with opamp-sharing architectures. The proposed BII technique does not need an additional preamplifier stage or need to sacrifice signal swing, as do other opamp summing node resetting (OSNR) techn... View full abstract»

• ### Design of a 24-GHz CMOS VCO With an Asymmetric-Width Transformer

Publication Year: 2010, Page(s):173 - 177
Cited by:  Papers (50)  |  Patents (2)
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A K-band CMOS voltage-controlled oscillator (VCO) is implemented with a 0.18- ??m radio frequency CMOS process. For low supply voltage operation, a transformer-feedback topology using a transformer is proposed. The analysis of the transformer-feedback VCO is presented. This shows that the inductance ratio of the transformer must be optimized, and asymmetric-width transformers allow the easy optimi... View full abstract»

• ### A 1.62/2.7-Gb/s Adaptive Transmitter With Two-Tap Preemphasis Using a Propagation-Time Detector

Publication Year: 2010, Page(s):178 - 182
Cited by:  Papers (6)
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A 1.62/2.7-Gb/s adaptive transmitter with two-tap preemphasis is presented. The tap coefficients are adjusted by detecting the propagation time through the channel with different lengths. This adaptive transmitter is fabricated in 0.13-??m CMOS technology, and the core area occupies 0.25 ?? 0.15 mm2. The maximum power consumption from a 1.2-V supply is 32.4 mW at 2.7 Gb/s. For a 40-in F... View full abstract»

• ### Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM

Publication Year: 2010, Page(s):183 - 187
Cited by:  Patents (1)
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Single-transistor floating-body RAM (FB-RAM) cells present a promising alternative for scalable high-density storage since both access and storage elements are implemented using a single FET-based device. Unlike embedded dynamic RAM (eDRAM) technology, the concept is fully scalable with decreasing technology nodes. However, to make the concept truly usable, special biasing conditions of the device... View full abstract»

• ### A 122-mW Low-Power Multiresolution Spectrum-Sensing IC With Self-Deactivated Partial Swing Techniques

Publication Year: 2010, Page(s):188 - 192
Cited by:  Papers (13)
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A low-power multiresolution spectrum-sensing (LP-MRSS) IC utilizing self-deactivated partial swing techniques is fabricated in 0.18-??m complementary metal-oxide-CMOS technology. The LP-MRSS is composed of a low-power digital window generator, analog correlators, low-power pipeline analog-to-digital converters, and a fast-sweeping frequency synthesizer. The LP-MRSS dissipates 122 mW at a 1.8-V sup... View full abstract»

• ### An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter

Publication Year: 2010, Page(s):193 - 197
Cited by:  Papers (22)  |  Patents (5)
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A new linearization scheme is proposed, which compensates for nonlinear distortions experienced in the amplitude-modulation path of a digital polar EDGE transmitter integrated in a 65-nm CMOS transceiver system-on-chip (SoC) based on the Digital RF Processor (DRP) technology. The measured amplitude and phase distortions are stored in lookup tables and used for predistortion without requiring inver... View full abstract»

• ### Improved Area-Efficient Weighted Modulo $2^{n} + 1$ Adder Design With Simple Correction Schemes

Publication Year: 2010, Page(s):198 - 202
Cited by:  Papers (12)
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In this brief, we proposed improved area-efficient weighted modulo 2n + 1 adders. This is achieved by modifying existing diminished-1 modulo 2n + 1 adders to incorporate simple correction schemes. Our proposed adders can produce modulo sums within the range {0, 2n}, which is more than the range {0, 2n - 1} produced by existing diminished-1 modulo 2n + 1 adders. W... View full abstract»

• ### Pseudorandom Bit Generation Using Coupled Congruential Generators

Publication Year: 2010, Page(s):203 - 207
Cited by:  Papers (7)
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In this brief, we propose the generation of a pseudorandom bit sequence (PRBS) using a comparative linear congruential generator (CLCG) as follows. A bit ??1?? is output if the first linear congruential generator (LCG) produces an output that is greater than the output of the second LCG, and a bit ??0?? is output otherwise. Breaking this scheme would require one to obtain the seeds of the two inde... View full abstract»

• ### Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes

Publication Year: 2010, Page(s):208 - 212
Cited by:  Papers (2)
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This brief analyzes the circuit-induced challenges to reliability and write current scaling of spin-torque-transfer random access memory (STTRAM). We show that, at sub-90-nm nodes, increased transistor leakage increases the probability of incorrect sensing requiring a higher read current. However, a higher read current can increase the read disturb failure, particularly with a reduced write curren... View full abstract»

• ### Master–Slave Synchronization of Fourth-Order Lü Chaotic Oscillators via Linear Output Feedback

Publication Year: 2010, Page(s):213 - 217
Cited by:  Papers (15)
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We solve the problem of master-slave synchronization of fourth-order Lu's hyperchaotic systems via feedback control. We use only one control input that enters in the slave system. We show that this simple feedback suffices to synchronize both systems exponentially fast. We provide a proof of stability and convergence (hence, that synchronization takes place) via Lyapunov's second stability ... View full abstract»

• ### A Design-Oriented Combined Approach for Bifurcation Prediction in Switched-Mode Power Converters

Publication Year: 2010, Page(s):218 - 222
Cited by:  Papers (48)
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In this brief, two different approaches are combined for studying the stability of a buck switching power dc-dc converter and for predicting its bifurcations. Instability indexes derived from both approaches are combined to get a complete design-oriented perspective of bifurcation analysis in terms of practical circuit parameter and to show the effect of each parameter on the system behavior. The ... View full abstract»

• ### Nondegeneracy Conditions for Active Memristive Circuits

Publication Year: 2010, Page(s):223 - 227
Cited by:  Papers (22)
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This brief presents a characterization of nondegenerate circuits with active memristors, i.e., memristors with a negative memductance at certain operating ranges. The analysis proceeds by characterizing index-one configurations in several differential-algebraic models of active memristive circuits. We apply tree-based techniques to the analysis of nodal analysis models and then extend this approac... View full abstract»

• ### A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method

Publication Year: 2010, Page(s):228 - 232
Cited by:  Papers (7)
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This brief presents a data-pattern-tolerant adaptive equalizer using the spectrum balancing method. In addition to a high-frequency boost control loop, this equalizer has a corner frequency control loop to guarantee its accurate adaptation for various data patterns and data rates. Measured results show that the jitter of the eye is reduced by a maximum of 37% when compared to the previous spectrum... View full abstract»

• ### An Energy-Efficient Error Correction Scheme for IEEE 802.15.4 Wireless Sensor Networks

Publication Year: 2010, Page(s):233 - 237
Cited by:  Papers (16)
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In this paper, we validate a novel augmentation to the physical layer (PHY) of the IEEE 802.15.4 standard for wireless sensor networks. This augmentation implements interleaving and forward error correction (FEC) encoding within sensor node transmitters, facilitating a significant reduction in their transmission energy. We detail the design, parameterization, and implementation of this FEC encoder... View full abstract»

• ### An Efficiency-Enhanced DCM Buck Regulator With Improved Switching Timing of Power Transistors

Publication Year: 2010, Page(s):238 - 242
Cited by:  Papers (25)
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This brief presents circuit techniques to improve the power efficiencies of a discontinuous-conduction mode (DCM) buck regulator for portable applications. A switched-capacitorcomparator-based adaptive dead-time control is developed to provide fast and accurate sensing and comparison for optimizing the switching timing of power transistors and thus simultaneously minimizing the power losses caused... View full abstract»

• ### 2010 IEEE international symposium on circuits and systems

Publication Year: 2010, Page(s): 243
| |PDF (674 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

Publication Year: 2010, Page(s): 244
| |PDF (33 KB)
• ### IEEE Circuits and Systems Society Information

Publication Year: 2010, Page(s): C3
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## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org