# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 35

Publication Year: 2010, Page(s):C1 - C4
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2010, Page(s): C2
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• ### Significant Effect of Emitter Area on the Efficiency, Stability and Reliability of Picosecond Switching in a GaAs Bipolar Transistor Structure

Publication Year: 2010, Page(s):733 - 741
Cited by:  Papers (5)
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A drastic reduction in the residual voltage (from ~ 100 V to a few volts) and a significant (factor of ~ 2) increase in the dU/dt switching rate is demonstrated experimentally in the superfast ( ~ 200 ps) avalanche switching of a GaAs bipolar junction transistor with increased emitter area. This result is not a trivial one as only a small number of co... View full abstract»

• ### Small-Signal Response of Inversion Layers in High-Mobility $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs Made With Thin High- $kappa$ Dielectrics

Publication Year: 2010, Page(s):742 - 748
Cited by:  Papers (64)
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Ultrahigh-mobility compound semiconductor-based MOSFETs and quantum-well field-effect transistors could enable the next generation of logic transistors operating at low supply voltages since these materials exhibit excellent electron transport properties. While the long-channel In0.53 Ga0.47As MOSFETs exhibit promising characteristics with unpinned Fermi level at the InGaAs-d... View full abstract»

• ### Reduction of Low-Temperature Nonlinearities in Pseudomorphic AlGaAs/InGaAs HEMTs Due to Si-Related DX Centers

Publication Year: 2010, Page(s):749 - 754
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The linearity of conventional pseudomorphic AlGaAs/InGaAs/AlGaAs high-electron mobility transistors with planar doping in the AlGaAs layers is shown to degrade at low temperatures down to -40Â°C, as measured by the adjacent-channel power ratio under wideband code-division multiple-access modulation. A modified structure, in which the planar Si doping layers are placed within thin single GaAs quant... View full abstract»

• ### Bilayer Pseudospin Field-Effect Transistor: Applications to Boolean Logic

Publication Year: 2010, Page(s):755 - 764
Cited by:  Papers (23)
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We have recently proposed a new type of bilayer graphene-based transistor for ultralow-power (perhaps 1000 times less compared with CMOS) room-temperature operation, namely, the bilayer pseudospin field-effect transistor (BiSFET). BiSFET operation is based on gated exciton-condensate-enhanced tunneling. Here, we discuss implementation, operation, and predicted power consumption of BiSFET-based Boo... View full abstract»

• ### Numerical Study of Lightly Doped Drain and Source Carbon Nanotube Field Effect Transistors

Publication Year: 2010, Page(s):765 - 771
Cited by:  Papers (36)
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In this paper, we investigate the transport properties of carbon nanotube field-effect transistors (CNTFETs), with a nonequilibrium Green's function (NEGF) method. Tunneling leakage currents with respect to gate voltages are known effects for MOSFET-like CNTFETs (MOSCNTs). To minimize this phenomenon, we have proposed a structure with a simple modification of the MOSCNT by using lightly doped regi... View full abstract»

• ### Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs

Publication Year: 2010, Page(s):772 - 781
Cited by:  Papers (14)
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In this paper, we demonstrate analytical device models and a unique subcircuit approach to physically and accurately model the dopant-segregated Schottky (DSS) gate-all-around (GAA) Si-nanowire (SiNW) MOSFETs. The direct current characteristics of the DSS GAA SiNW MOSFETs are investigated through numerical simulations and fabricated devices. Transport mechanisms are studied and explained with nume... View full abstract»

• ### High-Performance Long-Wavelength Infrared HgCdTe Focal Plane Arrays Fabricated on CdSeTe Compliant Si Substrates

Publication Year: 2010, Page(s):782 - 787
Cited by:  Papers (6)
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At the U.S. Army Research Laboratory, a new ternary semiconductor system CdSexTe1-x,/Si(211) is being investigated as an alternative substrate to bulk-grown CdZnTe substrates for HgCdTe growth by molecular beam epitaxy. Long-wavelength (LW) photovoltaic devices fabricated on this compliant substrate material show diffusion limited performance at 78 K, indicating a high-qualit... View full abstract»

• ### Performance Simulation and Architecture Optimization for CMOS Image Sensor Pixels Scaling Down to 1.0 $muhbox{m}$

Publication Year: 2010, Page(s):788 - 794
Cited by:  Papers (11)
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As the pixel dimensions of complementary metal-oxide-semiconductor sensors are approaching the wavelength of visible light, significant diffraction effects occur in the pixel architecture region, resulting in decreased optical efficiency and increased spatial crosstalk. By introducing the finite-difference time-domain approach, the performance of the typical 1.75-, 1.35-, and 1.05-μm pitch... View full abstract»

• ### Simulation of Statistical Aspects of Charge Trapping and Related Degradation in Bulk MOSFETs in the Presence of Random Discrete Dopants

Publication Year: 2010, Page(s):795 - 803
Cited by:  Papers (30)
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The distribution of fractional current change and threshold voltage shift in an ensemble of realistic 35 nm bulk negative-channel metal-oxide-semiconductor field-effect transistors caused by charge trapping on stress-generated defect states at the Si/SiO2 interface is studied using 3-D statistical Â¿atomisticÂ¿ simulations. The simulations take into account the underlying random discret... View full abstract»

• ### Scaling the Suspended-Gate FET: Impact of Dielectric Charging and Roughness

Publication Year: 2010, Page(s):804 - 813
Cited by:  Papers (10)
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Suspended gate field-effect transistors (SG-FETs) with switching gates are interesting as digital logic switches because of their high I on/I off current ratio and their infinite subthreshold slope. However, the limits of scalability of the SG-FETs are still unclear. This paper investigates two effects that could limit scaling: the dielectric charging and the di... View full abstract»

• ### Investigation of LOCOS- and Polysilicon-Bound Diodes for Robust Electrostatic Discharge (ESD) Applications

Publication Year: 2010, Page(s):814 - 819
Cited by:  Papers (22)
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In this paper, the current-carrying and voltage-clamping capabilities of LOCal Oxidation of Silicon (LOCOS)- and polysilicon-bound diodes are first investigated. Comparison of these capabilities leads to the conclusion that the polysilicon-bound diode is more suited for electrostatic discharge (ESD) protection applications. Then, to achieve an optimal diode structure for ESD applications, the effe... View full abstract»

• ### Influence of Channel and Gate Engineering on the Analog and RF Performance of DG MOSFETs

Publication Year: 2010, Page(s):820 - 826
Cited by:  Papers (70)
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The design of analog and RF circuits in CMOS technology has become increasingly more difficult as device modeling faces new challenges in the deep-submicrometer regime and emerging circuit applications. In this paper, we investigate the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications. The gate engineering ... View full abstract»

• ### Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions

Publication Year: 2010, Page(s):827 - 834
Cited by:  Papers (112)
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This paper presents a pseudo-2-D surface potential model for the double-gate tunnel field-effect transistor (DG-TFET). Analytical expressions are derived for the 2-D potential, electric field, and generation rate, and used to numerically extract the tunneling current. The model predicts the device characteristics for a large range of parameters and allows gaining insight on the device physics. The... View full abstract»

• ### Local $V_{rm th}$ Variability and Scalability in Silicon-on-Thin-BOX (SOTB) CMOS With Small Random-Dopant Fluctuation

Publication Year: 2010, Page(s):835 - 845
Cited by:  Papers (62)
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The silicon on thin buried oxide (SOTB) has the smallest V th variation among planar CMOS due to a low-dose channel. This study focuses on evaluating local variability components and searching for the dominant factor after reducing random-dopant fluctuation (RDF) by decreasing impurities in the channel. Improving short-channel-effect immunity is important to reduce both the globa... View full abstract»

• ### Nonsaturating Drain Current Characteristic in Short-Channel Amorphous-Silicon Thin-Film Transistors

Publication Year: 2010, Page(s):846 - 854
Cited by:  Papers (10)
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Nonsaturating drain current characteristics are analyzed in terms of the channel length modulation (CLM) and the self-heating effect. According to this analysis, the nonsaturating drain current arises if the effective channel length is sufficiently reduced such that the CLM effect leads to a superlinear increase of the drain current beyond saturation. The extracted CLM parameter was around Â¿' = 1... View full abstract»

• ### Modeling the Independent Double Gate Transistor in Accumulation Regime for 1TDRAM Application

Publication Year: 2010, Page(s):855 - 865
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This paper details the modeling of a one-transistor dynamic random-access memory (1TDRAM) based on an independent double-gate device. A pseudo-2-D compact model of memory operations and dynamic behavior of data retention is proposed. The physical mechanisms involved are calculated through the accumulated charge in the body modulated by quantum effects related to thin silicon films. The resulting c... View full abstract»

• ### The High-Mobility Bended n-Channel Silicon Nanowire Transistor

Publication Year: 2010, Page(s):866 - 876
Cited by:  Papers (30)  |  Patents (1)
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This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabr... View full abstract»

• ### Effect of Deep-Level Defects on Surface Recombination Velocity at the Interface Between Silicon and Dielectric Films

Publication Year: 2010, Page(s):877 - 889
Cited by:  Papers (3)
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The surface recombination velocity (SRV) characteristic of deep-level defects at Si interfaces with dielectric thin films was obtained from conductance measurements on metal-insulator-semiconductor capacitor (MISCAP) devices. The dielectrics in contact with Si were thermal SiO2 (Tox), chemical SiO2, and atomic layer deposition (ALD) Al2O3, which were ann... View full abstract»

• ### A Novel Method of MOSFET Series Resistance Extraction Featuring Constant Mobility Criteria and Mobility Universality

Publication Year: 2010, Page(s):890 - 897
Cited by:  Papers (11)
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A method of MOSFET series resistance extraction is established in this paper. The core of this method relies on the constant mobility criteria, while for different gate lengths, it preserves the shape of universal mobility curves in the high-vertical-field regime. Consequently, the series resistance of a MOSFET can be extracted in an analytical and self-consistent manner, achieved without the know... View full abstract»

• ### Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High- $k$ Dielectrics

Publication Year: 2010, Page(s):898 - 904
Cited by:  Papers (17)
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Achieving low p-channel metal-oxide-semiconductor (PMOS) threshold voltages with metal gates and high-k dielectrics is challenging with conventional gate-first complimentary metal-oxide-semiconductor process integration. This study, for the first time, explores the tradeoffs in using different combinations of thin-strained Si1 - x Gex channels, boron counterdopings,... View full abstract»

• ### Origins of Performance Enhancement in Independent Double-Gated Poly-Si Nanowire Devices

Publication Year: 2010, Page(s):905 - 912
Cited by:  Papers (2)
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In this paper, we characterize and compare the characteristics of a poly-Si nanowire (NW) device with independent double-gated configuration under different operation modes. In the device, the tiny NW channels are surrounded by an inverted-T-shaped gate and a top gate. It is found that the device under double-gate (DG) mode exhibits significantly better performance with respect to the two single-g... View full abstract»

• ### Investigation of Random Telegraph Noise in Gate-Induced Drain Leakage and Gate Edge Direct Tunneling Currents of High-$k$ MOSFETs

Publication Year: 2010, Page(s):913 - 918
Cited by:  Papers (17)
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Random telegraph noise (RTN) in gate-induced drain leakage (GIDL) and gate edge direct tunneling (EDT) leakage currents under GIDL bias conditions were characterized in MOSFETs with a high-k gate dielectric for the first time. The RTNs were analyzed through systematic measurement and calculation. The results indicate that a high-current state in a GIDL current can be attributed to electron ... View full abstract»

• ### Short-Circuit Capability of SiC Buried-Gate Static Induction Transistors: Basic Mechanism and Impacts of Channel Width on Short-Circuit Performance

Publication Year: 2010, Page(s):919 - 927
Cited by:  Papers (6)  |  Patents (2)
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Fundamental short-circuit operations of silicon carbide static induction transistors with buried-gate structures (BGSITs) were experimentally clarified, with subsequent device simulations. The impacts of channel width and source length on short-circuit capabilities were investigated. In particular, a design concept of the channel width was proposed to improve the short-circuit energy without a ser... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy