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IEEE Design & Test of Computers

Issue 2 • March-April 2010

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Displaying Results 1 - 23 of 23
  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • [Front cover]

    Publication Year: 2010, Page(s): c2
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  • Call for Papers

    Publication Year: 2010, Page(s): 1
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  • Call for Papers

    Publication Year: 2010, Page(s): 17
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  • Toc 
  • Table of Contents

    Publication Year: 2010, Page(s):2 - 3
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  • Compact variability modeling to the rescue

    Publication Year: 2010, Page(s): 4
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  • [Masthead]

    Publication Year: 2010, Page(s): 5
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  • Guest Editors' Introduction: Compact Variability Modeling in Scaled CMOS Design

    Publication Year: 2010, Page(s):6 - 7
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  • Modeling Process Variability in Scaled CMOS Technology

    Publication Year: 2010, Page(s):8 - 16
    Cited by:  Papers (48)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (900 KB) | HTML iconHTML

    Process variability has become a critical issue in scaled CMOS design. This article provides a comprehensive view on the predominant variation sources in sub-90-nm devices, their impact on device and circuit performance, and various modeling approaches for statistical circuit analysis. View full abstract»

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  • Layout Proximity Effects and Modeling Alternatives for IC Designs

    Publication Year: 2010, Page(s):18 - 25
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1132 KB) | HTML iconHTML

    Layout-dependent variations significantly affect device modeling, model extraction, and design solutions. A novel approach is proposed in this article to seamlessly integrate physical models of lithography, strained Si, and ion implantation processes, with layout geometry for efficient model generation. View full abstract»

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  • Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP

    Publication Year: 2010, Page(s):26 - 35
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (877 KB) | HTML iconHTML

    The strategy to generate statistical model parameters is essential for variability-aware design. Based on 3D atomistic simulation results, this article evaluates the accuracy of statistical parameter generation for two industry-standard compact device models. View full abstract»

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  • Extensions to Backward Propagation of Variance for Statistical Modeling

    Publication Year: 2010, Page(s):36 - 43
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1136 KB) | HTML iconHTML

    Correlating the statistics of process parameters with the statistics of electrical performance is a vital task in statistical modeling. This article describes a more general form of the backward propagation of variance (BPV) method, a numerical technique for iteratively solving the statistics of process parameters from the statistics of electrical performance within the behavior of models encapsul... View full abstract»

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  • Compact Modeling of Variation in FinFET SRAM Cells

    Publication Year: 2010, Page(s):44 - 50
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (729 KB) | HTML iconHTML

    FinFET technology is a possible solution to achieve a better power/performance trade-off for SRAM cells. This article provides a comprehensive analysis of the variations in FinFET devices, their impact on SRAM stability, and a statistical design procedure for FinFET SRAM cells. View full abstract»

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  • Power Supply Noise: A Survey on Effects and Research

    Publication Year: 2010, Page(s):51 - 67
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (763 KB) | HTML iconHTML

    As technology scales to 32 nm and functional frequency and density continue to rise, PSN effects, which can reduce a circuit's noise immunity and could lead to failures, pose new challenges to chip manufacturers and foundries. This article provides an overview of low-power and delay testing, and surveys ongoing research for analyzing and dealing with PSN effects during delay test and timing analys... View full abstract»

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  • NSF Workshop on EDA: Past, Present, and Future (Part 1)

    Publication Year: 2010, Page(s):68 - 74
    Cited by:  Papers (2)
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  • Conference reports

    Publication Year: 2010, Page(s): 75
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  • CEDA Currents

    Publication Year: 2010, Page(s):76 - 78
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  • Design Automation Technical Committee Newsletter

    Publication Year: 2010, Page(s): 79
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  • Test Technology TC Newsletter

    Publication Year: 2010, Page(s):80 - 81
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  • A career in system-level design research [review of "Embedded System Design: Modeling, Synthesis, and Verification (Gajski, D.D. et al; 2009)]

    Publication Year: 2010, Page(s):82 - 83
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  • 'Tis the gift to be simple

    Publication Year: 2010, Page(s):84 - 86
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  • [Advertisement - Back cover]

    Publication Year: 2010, Page(s): c3
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  • [Advertisement - Back cover]

    Publication Year: 2010, Page(s): c4
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty