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Micro, IEEE

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Micro, IEEE

Issue 1 • Date Jan.-Feb. 2010

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[Front cover]

[Front cover]

Contents

Call for Applications for Editor in Chief

The Next Chapter at Google [Micro Economics]

Guest Editor's Introduction: Top Picks from the Computer Architecture Conferences of 2009

iCFP: Tolerating All-Level Cache Misses in In-Order Processors

Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures

A Task-Centric Memory Model for Scalable Accelerator Architectures

DMP: Deterministic Shared-Memory Multiprocessing

Making Address-Correlated Prefetching Practical

Accelerating Critical Section Execution with Asymmetric Multicore Architectures

Per-Thread Cycle Accounting

AnySP: Anytime Anywhere Anyway Signal Processing

Gate-Level Information-Flow Tracking for Secure Architectures

Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity

Architectural Implications of Nanoscale-Integrated Sensing and Computing

Gordon: An Improved Architecture for Data-Intensive Applications

Phase-Change Technology and the Future of Main Memory

Technical Writing [review of Managing Writers: A Real World Guide to Managing Technical Documentation (Hamilton, R.; 2009)]

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