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Advanced Packaging, IEEE Transactions on

Issue 1 • Date Feb. 2010

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  • Table of contents

    Publication Year: 2010 , Page(s): C1 - 1
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  • IEEE Transactions on Advanced Packaging publication information

    Publication Year: 2010 , Page(s): C2
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  • Noise Isolation in Mixed-Signal Systems Using Alternating Impedance Electromagnetic Bandgap (AI-EBG) Structure-Based Power Distribution Network (PDN)

    Publication Year: 2010 , Page(s): 2 - 12
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1545 KB) |  | HTML iconHTML  

    This paper presents efficient noise isolation and suppression method in mixed-signal systems using alternating impedance electromagnetic bandgap (AI-EBG) structure-based power distribution network (PDN). Currently, split planes are used for isolation in mixed-signal systems for isolating sensitive RF/analog circuits from noisy digital circuits. However, split planes show good isolation only at low frequencies due to electromagnetic coupling through the gap. The AI-EBG structure-based PDN presented in this paper provides excellent isolation (-80 dB ~ -100 dB) in the frequency range of interest by suppressing almost all possible electromagnetic modes. The AI-EBG structure has been integrated into a mixed-signal test vehicle to demonstrate the isolation level achievable. The ability of the AI-EBG structure to suppress switching noise has been quantified in this paper. The AI-EBG structure provided greater than 100 dB of isolation in passive S-parameter measurement and suppressed in-band noise down to -88 dBm of isolation in a functional test. View full abstract»

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  • Escape Routing in Modern Area Array Packaging: An Analysis of Need, Trend, and Capability

    Publication Year: 2010 , Page(s): 13 - 18
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    With the increasing complexity in the die and package designs and ever increasing cost pressure in today's microelectronic industry, the design for input/output (I/O) routing has assumed a vital role in the overall product design. This scenario is primarily driven by the increase in the I/O terminal counts in both die and package. Several authors have already described the possibility of using various escape routing models in order to maximize the number of I/Os in a given area. However, these models suffer from many drawbacks and fail to address the importance of processing factors and the actual manufacturing conditions. Therefore, a new design guideline for escape routing has been developed to achieve the maximum I/O density under the actual manufacturing, processing and cost related constraints. The correlation between the real world constraints and their impact on I/O routing has been explored and used as a foundation for developing design guidelines. This approach has been presented through a comprehensive case study that covers various design scenarios, provides the right set of real world trade-offs that need to be considered and simultaneously highlights the drawbacks in existing models. View full abstract»

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  • Defect Detection of Flip Chip Solder Bumps With Wavelet Analysis of Laser Ultrasound Signals

    Publication Year: 2010 , Page(s): 19 - 29
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2209 KB) |  | HTML iconHTML  

    Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages, and ball grid arrays, chips/packages are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. Solder bumps hidden between the chips/packages and the substrate/board are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometer techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chip packages, chip scale packages and land grid arrays. The system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response in nanometer scale on the package surface is measured using the interferometer technique. In this paper, wavelet analysis of laser ultrasound signals is presented and compared to previous signal processing methods, such as error ratio and correlation coefficient. The results show that wavelet analysis increases measurement sensitivity for inspecting solder bumps in electronic packages. Laser ultrasound inspection results are also compared to X-ray results. In particular, this paper discusses defect detection for a 6.35 mm ?? 6.35 mm ?? 0.6 mm PB18 flip chip package and flip chip package (??SiMAF??) with 24 lead-free solder bumps. These two types of flip chip specimens are both nonunderfilled. View full abstract»

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  • Design and Fabrication of 0/1-Level RF-Via Interconnect for RF-MEMS Packaging Applications

    Publication Year: 2010 , Page(s): 30 - 36
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2355 KB) |  | HTML iconHTML  

    This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz. View full abstract»

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  • Novel 3-D Coaxial Interconnect System for Use in System-in-Package Applications

    Publication Year: 2010 , Page(s): 37 - 47
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1954 KB) |  | HTML iconHTML  

    This paper presents the design and demonstration of a novel die-to-die interconnect system for deployment in system-in-package (SiP) applications with adjacent or stacked-die configurations. The interconnect system consists of miniature coaxial cables that are mounted to a standard Silicon substrate using an etched trench along the perimeter of the die. The trench serves as a self-alignment feature for both the signal and ground contacts in addition to providing mechanical strain relief for the coaxial cable. The system is designed to interface on-chip coplanar transmission lines to off-chip coaxial transmission lines to produce a fully impedance matched system. This approach promises to dramatically improve the electrical performance of high-speed, die-to-die signals by eliminating impedance discontinuities, providing a shielded signal path, and providing a low-impedance return path for the switching signal. The new interconnect system is designed to be selectively added to a standard wire bond pad configuration using an incremental etching process. This paper describes the design process for the new approach including the fabrication sequence to create the transition trenches. Finite-element analysis is performed to evaluate the electrical performance of the proposed system. View full abstract»

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  • Analysis of Adhesion and Fracture Energy of Nano-Particle Silver in Electronics Packaging Applications

    Publication Year: 2010 , Page(s): 48 - 57
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2115 KB) |  | HTML iconHTML  

    Nano-particle silver (NPS) conductors are increasingly being investigated for package level electronics applications. Unlike traditional thick film materials and conductive inks, nano-particle conductors often do not incorporate compounds to promote interfacial adhesion such as binders used in thick films and polymer adhesives used in conductive inks as these adhesion promoters can degrade the electrical performance. The NPS is concerned with low adhesion to most of processed polymer surface such as liquid crystal polymer (LCP), polyimide, and benzocyclobutene (BCB). Moreover, the adhesion mechanism of NPS has not been identified yet. Thus, as a first step to identify NPS adhesion mechanism and thus, to improve NPS adhesion, quantitative measurement of the adhesion strength of NPS is necessary. Since conventional adhesion test methods are not directly applicable to thin (~ 2 ??m) NPS film adhesion test, a new adhesion test method is developed in this paper to estimate the adhesion strength of NPS films. The newly developed adhesion test method is called modified button shear test (MBST) because it modifies the conventional button shear test and integrates the generally known die shear test. The MBST is used for measuring not only interfacial bond strength, but also interfacial fracture energy. The interfacial bond strength in tension and the interfacial fracture energy of NPS with LCP substrate measured by MBST are 24.4 MPa and 17.2 J/m2, respectively. The MBST is generic in nature and can be extended to other thin films adhesion test for measuring interfacial bond strength and interfacial fracture energy. View full abstract»

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  • Recrystallization, Electric Flame-Off Characteristics, and Electron Backscatter Diffraction of Copper Bonding Wires

    Publication Year: 2010 , Page(s): 58 - 63
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1205 KB) |  | HTML iconHTML  

    In the present study, the neck fracture properties of annealed wire with ¿ = 20 ¿m (0.8 mil) at 200°C ~ 300°C for 1 h and unannealed wire were compared. The microstructural characteristics, the mechanical properties and the texture transition using electron back scatter diffraction methods before and after an electric flame-off (EFO) process were also studied. Experimental results indicate that the annealing temperatures of more than 225°C, the 20 ¿m copper wires possessed a fully annealed structure, the tensile strength and the hardness decreased, and the elongation was raised. Through recrystallization, the matrix structure transferred from long, thin grains to equiaxed grains and a few annealed twins. The microstructure of the free air ball (FAB) after an EFO process consisted of column-like grains, and grew from the heat-affected zone (HAZ) to the Cu ball. For the 225°C annealed and unannealed wires, their preferred orientations on the wire and the neck were ¿100¿//AD. Under the thermal effect of EFO, the orientation of the Cu balls were mainly ¿101¿//AD and ¿111¿//AD for annealed wires. Additionally, the hardness of the Cu balls and the strength of the neck sites of the EFO wires were able to affect the reliability of the copper wire bonding. View full abstract»

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  • Reliability Verification of Hermetic Package With Nanoliter Cavity for RF-Micro Device

    Publication Year: 2010 , Page(s): 64 - 71
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1672 KB) |  | HTML iconHTML  

    With the advance of high-performance and small-size microelectromechanical systems (MEMS) devices, wafer-level packaging has gained increased attention over the past few years. Most MEMS packages must protect the often-fragile mechanical structures against the environment and provide the interface for the interaction with the next level in the packaging hierarchy. It is obvious that stable performance and high reliability are essential requirements of a packaged device. In this paper, a novel hermetic package, called the WL-??P, recently developed for radio-frequency (RF)-filter and RF-duplexer, will be reviewed in terms of its construction, fabrication process, and electrical/mechanical performance. The package consists of a device wafer for a MEMS device and a cap wafer that has a micromachined cavity and through-wafer vias for electrical connections. The cap and device wafers are bonded to each other through a closed square loop of gold/tin eutectic solder at the peripheral edge. The via-in-cavity structure is designed in the cap substrate, with vertical via holes fabricated and fully electroplated with copper. The detailed design and fabrication technology of this new type of hermetically sealed package are presented with process flow. The performance evaluation and reliability results of a hermetic package will also be presented. The developed wafer-level hermetic package technology is able to fulfill today's requirements for hermetic and cost-effective packaging of high-speed RF-MEMS applications. View full abstract»

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  • Fine-Pitch Capabilities of the Flat Ultra-Thin Chip Packaging (UTCP) Technology

    Publication Year: 2010 , Page(s): 72 - 78
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1021 KB) |  | HTML iconHTML  

    This paper describes the fine-pitch interconnection capabilities of the ultra-thin chip packaging (UTCP) technology, a technology under development for embedding thin chips in a flexible polyimide (PI) substrate. It allows for fully flexible electronics, as the rigid chips are thinned down to 20-30 ??m, at which point they become truly flexible themselves. This way, instead of just a flexible substrate with rigid components assembled on top, the entire circuitry can be incorporated inside a 30-40 ??m thin chip package. The paper briefly introduces the technology's background with a short description of the fabrication process. Building on the developments already achieved, some further optimizations are discussed, and the technology is tested for its fine-pitch interconnection capabilities using test chips with four-point probe and daisy chain patterns, with a pitch down to 40 ??m. The possibility to package several chips in the same substrate is investigated, as well, and finally an outlook on future experiments is briefly discussed. View full abstract»

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  • Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips

    Publication Year: 2010 , Page(s): 79 - 87
    Cited by:  Papers (28)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1677 KB) |  | HTML iconHTML  

    Power dissipation in microprocessors is projected to reach a level that may necessitate chip-level liquid cooling in the near future. An on-chip microchannel heat sink can reduce the total thermal interfaces between an integrated circuit chip and the convective cooling medium and therefore yield smaller junction-to-ambient thermal resistance. This paper reports the fabrication, assembly, and testing of a silicon chip with complementary metal-oxide-semiconductor process compatible microchannel heat sink and thermofluidic chip input/output (I/O) interconnects fabricated using wafer-level batch processing. Ultra-small form factor, low-cost fabrication and assembly (system integration) are achieved for 2D and 3D chips, as the microchannel heat sink is fabricated directly on back-side of each chip. Through-wafer electrical and fluidic vias are used to interconnect the monolithically integrated microchannel heat sink to thermofluidic chip I/O interconnections. The feasibility of the novel fluidic I/O interconnect is demonstrated through preliminary thermal resistance measurements. View full abstract»

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  • Rapid Assessment of BGA Fatigue Life Under Vibration Loading

    Publication Year: 2010 , Page(s): 88 - 96
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (874 KB) |  | HTML iconHTML  

    Ball grid array (BGA) packages are a relatively package type and have rapidly become the package style of choice. Much high density, high I/O count semiconductor devices are now only offered in this package style. Designers are naturally concerned about the robustness of BGA packages in a vibration environment when their experience base is with products using more traditional compliant gull or J leaded surface mount packages. Because designers simply do not have the experience, tools are needed to assess the vibration fatigue life of BGA packages during early design stages and not have to wait for product qualification testing, or field returns, to determine if a problem exists. This paper emphasizes a rapid assessment methodology to determine fatigue life of BGA components. If time and money were not an issue, clearly one would use a general-purpose finite element program to determine the dynamic response of the printed circuit board (PCB) in the vibration environment. Once the response of the PCB was determined, one would determine the location and value of the critical stress in the component of interest. Knowing the critical stress, one would estimate the fatigue life from a damage model. The time required building the finite element analysis (FEA) model, conducting the analysis, and postprocess the results would take at least a few days to weeks. This is too time-consuming, except in the most critical applications. It is not a process that can be used in everyday design and what-if simulations. The rapid assessment approach proposed in this paper focuses on a physics of failure type approach to damage analysis and involves global and local modeling to determine the critical stress in the component of interest. A fatigue damage model then estimates the life. The entire fatigue life assessment is anticipated to be executed by an average engineer in real time and take only minutes to generate accurate results. View full abstract»

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  • Peridynamic Theory for Thermomechanical Analysis

    Publication Year: 2010 , Page(s): 97 - 105
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (857 KB) |  | HTML iconHTML  

    Thermomechanical modeling for interconnects and electronic packages is a difficult challenge, especially for material interfaces and films under 1 ??m dimension. Understanding and prediction of their mechanical failure require the simulation of material behavior in the presence of multiple length scales. However, the classical continuum theory is not capable of predicting failure without a posterior analysis with an external crack growth criteria and treats the interfaces having zero thickness. A new nonlocal continuum theory referred to as peridynamic theory offers the ability to predict failure at these length scales. This study presents a new response function as part of the peridynamic theory to include thermal loading. After validating this response function by comparing against the displacement predictions in benchmark problems against those of finite element method, the peridynamic theory is used to predict damage initiation and propagation in regions having dissimilar materials due to thermomechanical loading. View full abstract»

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  • Design and Analysis of Packaging Boxes for Flat Panel Displays

    Publication Year: 2010 , Page(s): 106 - 114
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1700 KB) |  | HTML iconHTML  

    A methodology of designing the packaging box based on the topology optimization technique is proposed. The packaging box is designed not only to protect the fragile liquid crystal display from damage but also take up a volume as small as possible in order to reduce the transport cost. In contrast to the traditional approach which minimizes the acceleration and/or the maximal stress of the panel contained in the packaging box, the proposed objective is to minimize simultaneously the predesignated natural frequency and the mean compliance of a packaging box subjected to a volume constraint. An algorithm which integrates the finite element software ANSYS used as the structural analysis tool, the optimization module based on the sequential linear programming, and a topology module, is developed to achieve the crashworthiness design of packaging box. The material properties as well as the finite element model of a packaging box are tested and validated experimentally. The packaging box after topology optimization is evaluated numerically by drop test simulations in terms of acceleration experienced by the panel and volume reduction of packaging box. For the specific example demonstrated, results show that an optimal layout of the packaging box not only has a smaller volume, 14.85% less than the packaging box used nowadays, but also reduce the maximal acceleration experienced by the panel by 8.9%. View full abstract»

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  • Parallel Simulation of Massively Coupled Interconnect Networks

    Publication Year: 2010 , Page(s): 115 - 127
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (852 KB) |  | HTML iconHTML  

    In a system containing high-speed interconnects, the presence of a large number of coupled lines seriously limits the ability to perform fast simulations. In this paper, a parallel algorithm is presented that allows for simulations of massively coupled interconnects to be performed efficiently. New methods based on physical and time-domain partitioning are developed to create parallelism during transient simulations of large coupled interconnects. In addition, the proposed method exploits the recently developed waveform relaxation techniques to decouple and parallelize the large coupled simulation problem. In this approach, for a simulation of nL lines run on nP processors, the computational complexity is O(nLnP -1). This provides considerable savings as opposed to O(nL ?? ), 3 ?? ?? ?? 4 for full coupled-line simulations. View full abstract»

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  • Correction of the Method of Images for Partial Inductance Calculations of QFP

    Publication Year: 2010 , Page(s): 128 - 138
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    The inapplicability of the method of images to partial inductance calculation within the magneto-quasi-static approximation has been shown by the authors in previous works. This concept is restated in this paper, and some correction terms for the application of the method of images are proposed. A partial inductance calculation technique based on potential theory is also proposed, which does not require the calculation of the current distribution, and is limited at present to infinite perfectly conducting planes. The proposed correction terms are verified with simple structures at first, and later with the calculation of the partial inductance matrix of a quad flat package. View full abstract»

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  • Active Heatsink Antenna for Radio-Frequency Transmitter

    Publication Year: 2010 , Page(s): 139 - 146
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1194 KB) |  | HTML iconHTML  

    This paper deals with the design of an active heat-sink antenna for radio-frequency transmitter. The antenna achieves electromagnetic and thermal functions by offering a suitable radiating pattern for transmission as high efficiency to remove the dissipated power within the transmitter by heat exchange to the surrounding medium. A test transmitter has been performed by combining a 2 GHz MESFET power amplifier in a conductor-backed coplanar wave-guide with a wire-fed patch heat-sink antenna connected to the ground plane. The active heat-sink antenna has been investigated by measurement and simulation. As expected, it was found that the antenna exhibits desirable electromagnetic performance as achieving an efficient thermal control by offering suitable operating temperature. A heat spreader connecting the transistor to the antenna, was especially developed to cause any significant influence on transmitter performance. The amplifier can deliver an output power as high as 5 W under natural convection with air at room temperature and atmospheric pressure. According to the temperature and direction of the antenna, thermal resistance of the transmitter was found between 6 and 8 K.W -1. The transmitter can thus operate over a wide temperature range without any additional cooling device. View full abstract»

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  • FPGA Based System for Open, Short, and RC Impedance Measurement

    Publication Year: 2010 , Page(s): 147 - 152
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (642 KB) |  | HTML iconHTML  

    This paper describes a time-based digital test system that may be used to detect opens, and shorts, as well as measure resistive and capacitive impedance of interconnect networks. The specific test implementation is customized through a field programmable gate array (FPGA). The use of an FPGA allows for reconfiguration of the test for many different interconnect verifications. The current progress of this system is demonstrated and experimental measurements are provided. View full abstract»

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  • On-Chip Coupled Transmission Line Modeling for Millimeter-Wave Applications Using Four-Port Measurements

    Publication Year: 2010 , Page(s): 153 - 159
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2295 KB) |  | HTML iconHTML  

    Transmission lines are fundamental elements in millimeter-wave circuits. In this paper, on-chip coupled transmission lines, fabricated in a commercial 0.18 ??m complementary metal-oxide semiconductor process, have been modeled, based on measured 50 GHz four-port scattering-parameters. The two-port open-short deembedding technique and thru deembedding method were successfully extended and applied to the four-port structures presented here. The accuracy of the deembedding techniques was verified by full-wave electromagnetic simulation. Based on the deembedded S-parameters, a SPICE-compatible equivalent circuit model of on-chip coupled transmission lines was extracted. Simulation and measurement results agree well over the entire frequency band from 100 MHz up to 50 GHz. View full abstract»

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  • LTCC Spiral Inductor Synthesis and Optimization With Measurement Verification

    Publication Year: 2010 , Page(s): 160 - 168
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1393 KB) |  | HTML iconHTML  

    In RF/microwave circuit design, inductor design is one of the most difficult and time-consuming tasks due to the tedious trial-and-error optimization process to achieve the target specifications such as inductance, quality factor and occupied space. This paper brings forward a fast spiral inductor synthesis method, which automatically generates physical layout of inductors according to electrical specifications. By fusion of substrate-aware partial element equivalent circuit (PEEC) model with nonlinear optimization engine, our modeling and synthesis strategies have been verified with industrial field solver and measurement results. Our calculation results got less than 7% error for inductance and less than 9% for quality factor as compared to the results from full-wave electromagnetic simulation software. This can provide a fast and good initial inductor design for designer. View full abstract»

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  • Wideband Circuit Model for Planar EBG Structures

    Publication Year: 2010 , Page(s): 169 - 179
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1344 KB) |  | HTML iconHTML  

    In this paper, we present a comprehensive equivalent circuit model to accurately characterize an important class of electromagnetic bandgap (EBG) structures over a wide range of frequencies. The model is developed based on a combination of lumped elements and transmission lines. The model presented here predicts with high degree of accuracy the dispersion diagram over a wide band of frequencies. Since the circuit model can be simulated using SPICE-like simulation tools, optimization of EBG structures to meet specific engineering criteria can be performed with high efficiency, thus saving significant computation time and memory resources. The model was validated by comparison to full-wave simulation results. View full abstract»

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  • Characterization of Next Generation Thin Low-K and Low-Loss Organic Dielectrics From 1 to 110 GHz

    Publication Year: 2010 , Page(s): 180 - 188
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1855 KB) |  | HTML iconHTML  

    This paper presents, for the first time, characterization results of next generation dielectric core and build up material called RXP, which has low dielectric constant (2.93-3.48) and low loss tangent (0.0037-0.006) up to 110 GHz. Unlike LCP, this material can be made ultra-thin with low processing temperature and is ideally suited for mobile applications. Causal models suitable for high frequency applications have been extracted by measuring the response of cavity resonators using vector network analyzer and surface profiler. View full abstract»

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  • Electromigration Characteristic of SnAg _{3.0} Cu _{0.5} Flip Chip Interconnection

    Publication Year: 2010 , Page(s): 189 - 195
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2548 KB) |  | HTML iconHTML  

    Electromigration is a reliability concern of microelectronic interconnections, especially for flip chip solder bump with high current density applied. This study shows that with the line-to-bump geometry in a flip chip solder joint, the current density changes significantly between the Al trace and the bump, while the current crowding effect generates more heat between them. This large Joule heating under high current density can enhance the migration of Sn atoms at the current entrance of the solder bump, and cause the void formation at the entrance point. The present study finds two kinds of electromigration failure modes at the cathode/chip side of the solder bump: the pancake-type and the cotton-type void. The experimental finding shows that the effects of polarity and tilting are key factors to observe in the electromigration behavior of SnAg3.0Cu0.5 solder bumps. Consequently, this study has designed a 3-D numerical model and a corresponding test vehicle to verify the numerical finding. The maximum current density is simulated through the finite element method to provide a better understanding of local heat and current crowding. This study finds that the current crowding ratio is reduced linearly while the void formation is increased. Furthermore, it is concluded that there is a linear relationship between the growth of the intermetallic compound (IMC) layer and the applied current density at the anode/substrate side. View full abstract»

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  • Electrical Characterization of Screen-Printed Circuits on the Fabric

    Publication Year: 2010 , Page(s): 196 - 205
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1480 KB) |  | HTML iconHTML  

    Fabrication methods of planar printed circuits on fabrics are introduced and their electrical characteristics are measured and analyzed. Wet patterning method like screen printing as well as dry process of sputtering are used to fabricate the patterned film electrodes on various types of fabrics. The minimum width of the patterns is 0.2 mm for screen printing and 0.1 mm for gold sputtering, and the typical sheet resistance is 134 m ??/??. Fabrication methods of capacitors of 1 pF-1 nF and inductors of 500 nH-1 ??H at 10 MHz on the fabrics are also introduced. Bonding and packaging of silicon chip directly on the fabric circuit board are proposed and their mechanical properties are investigated. The ac impedance of the transmission line is measured as 201-215 ?? with variation, and the time-domain reflectometry profile shows that the -3 dB frequency of the printed transmission line of 15 cm on the fabric is 80 MHz. A complete system composed of a fabric capacitor sensor input, a controller system-on-a-chip, and an LED array display is implemented on the fabric and its operation is demonstrated successfully. View full abstract»

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Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering