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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 3 • Date March 2010

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Table of contents

IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Editorial : New Associate Editor Appointments

Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew

Reducing SRAM Power Using Fine-Grained Wordline Pulsewidth Control

On the Latency and Energy of Checkpointed Superscalar Register Alias Tables

Crosstalk-Induced Delay, Noise, and Interconnect Planarization Implications of Fill Metal in Nanoscale Process Technology

DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In

Path Selection for Transition Path Delay Faults

Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits

FPGA Design for Timing Yield Under Process Variations

Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs

Interstratum Connection Design Considerations for Cost-Effective 3-D System Integration

Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback

A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise

Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning

Compressive Acquisition CMOS Image Sensor: From the Algorithm to Hardware Implementation

Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment

Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS

A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme

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