IEEE Design & Test of Computers

Issue 1 • Jan.-Feb. 2010

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Displaying Results 1 - 22 of 22
  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • [Front cover]

    Publication Year: 2010, Page(s): c2
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  • Call for Papers

    Publication Year: 2010, Page(s): 1
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  • Toc 
  • Table of Contents

    Publication Year: 2010, Page(s):2 - 3
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  • Design & Test in the new decade: Continuity and new directions

    Publication Year: 2010, Page(s):4 - 5
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  • [Advertisement]

    Publication Year: 2010, Page(s): 6
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  • [Masthead]

    Publication Year: 2010, Page(s): 7
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  • Guest Editors' Introduction: Confronting the Hardware Trustworthiness Problem

    Publication Year: 2010, Page(s):8 - 9
    Cited by:  Papers (2)
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  • A Survey of Hardware Trojan Taxonomy and Detection

    Publication Year: 2010, Page(s):10 - 25
    Cited by:  Papers (272)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1079 KB) | HTML iconHTML

    Editor's note:Today's integrated circuits are vulnerable to hardware Trojans, which are malicious alterations to the circuit, either during design or fabrication. This article presents a classification of hardware Trojans and a survey of published techniques for Trojan detection. View full abstract»

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  • Hardware Trojans in Wireless Cryptographic ICs

    Publication Year: 2010, Page(s):26 - 35
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3686 KB) | HTML iconHTML

    The article studies the problem of hardware Trojans in wireless cryptographic ICs. The objective is to design Trojans to leak secret information through the wireless channel. The authors investigate challenges related to detection for such Trojans and propose using statistical analysis of the side-channel signals to help detect them. View full abstract»

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  • Attacks and Defenses for JTAG

    Publication Year: 2010, Page(s):36 - 47
    Cited by:  Papers (28)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1369 KB) | HTML iconHTML

    JTAG is a well-known standard mechanism for in-field test. Although it provides high controllability and observability, it also poses great security challenges. This article analyzes various attacks and proposes protection schemes. View full abstract»

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  • Verifying Physical Trustworthiness of ICs and Systems 
  • Secure and robust error correction for physical unclonable functions

    Publication Year: 2010, Page(s):48 - 65
    Cited by:  Papers (89)  |  Patents (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (650 KB) | HTML iconHTML

    Physical unclonable functions (PUFs) offer a promising mechanism that can be used in many security, protection, and digital rights management applications. One key issue is the stability of PUF responses that is often addressed by error correction codes. The authors propose a new syndrome coding scheme that limits the amount of leaked information by the PUF error-correcting codes. View full abstract»

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  • Preventing IC Piracy Using Reconfigurable Logic Barriers

    Publication Year: 2010, Page(s):66 - 75
    Cited by:  Papers (70)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3002 KB) | HTML iconHTML

    Hardware metering to prevent IC piracy is a challenging and important problem. The authors propose a combinational locking scheme based on intelligent placement of the barriers throughout the design in which the objective is to maximize the effectiveness of the barriers and to minimize the overhead. View full abstract»

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  • Verification-Purpose Operating System for Microprocessor System-Level Functions

    Publication Year: 2010, Page(s):76 - 85
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3186 KB) | HTML iconHTML

    Microprocessor system-level functions that provide hardware support for software are difficult to verify on FPGA prototypes. Traditional FPGA verification involves running a general-purpose operating system such as Linux. However, such a GPOS is difficult to control, and debug is inefficient. The verification-purpose operating system, on the other hand, simplifies debug and is easy to control. VPO... View full abstract»

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  • CEDA Currents

    Publication Year: 2010, Page(s):86 - 87
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  • Design Automation Technical Committee Newsletter

    Publication Year: 2010, Page(s):88 - 89
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  • Test Technology TC Newsletter

    Publication Year: 2010, Page(s):90 - 91
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  • Conference Reports

    Publication Year: 2010, Page(s): 92
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  • Master numerical tasks with ease [review of Advanced Excel for Scientific Data Analysis, 2nd ed. (de Levie, R.; 2008)] [Book reviews]

    Publication Year: 2010, Page(s):93 - 95
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  • Variability: For headache and profit

    Publication Year: 2010, Page(s):96 - 98
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB) | HTML iconHTML

    The paper discusses hardware security. The author mention that there were best times and worst times for hardware security. Numerous factors facilitate, both qualitatively and quantitatively an essentially unlimited potential for attacks. Factors include an increasingly popular and profitable horizontal semiconductor business model, sharply reduced controllability and observability ultracheap sili... View full abstract»

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  • [Advertisement - Back cover]

    Publication Year: 2010, Page(s): c4
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  • [Advertisement - Back cover]

    Publication Year: 2010, Page(s): c3
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty