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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb. 2010

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  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Page(s): C2
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  • 2008 Best Paper Award

    Page(s): 1
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  • Introduction to the Special Section on Engineering and Technology Management

    Page(s): 2 - 3
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  • A GSPN-Based Approach to Stacked Chips Scheduling Problem

    Page(s): 4 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (471 KB) |  | HTML iconHTML  

    This paper discusses scheduling characteristics unique in stacked chips [including multichip package (MCP) and multidie package (MDP)] production process such as reentrant work flow and synchronization constraint. It also proposes a modeling and analytical framework for stacked chips assembly operations, which is based on the formal framework of generalized stochastic Petri net. This approach allows the seamless integration of the logical and timed dynamics of stacked chip assembly operations in a single representation. Furthermore, the proposed framework supports the analytical representation of the stacked chips scheduling problem as a mathematical programming formulation, which can be effectively solved to optimality through enumerative techniques. The framework presentation and its capabilities are elucidated by detailed application on a small system configuration for MCP. View full abstract»

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  • Hunting Down the Bubble Makers in Fabs

    Page(s): 13 - 20
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    Based on a simulated non volatile memory fab, we employ data-mining to identify and quantify the apparent causes of work in process bubbles along the process. The chosen bubble formalization methods proved able to detect the phenomenon and enabled its occurrence frequency to be forecasted. In the chosen environment, bubbles seem to be highly correlated with the utilization patterns of the process segment considered. View full abstract»

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  • Optimizing Your Position on the Operating Curve: How Can a Fab Truly Maximize Its Performance?

    Page(s): 21 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (682 KB) |  | HTML iconHTML  

    An empirically grounded model of a fab operating curve that is sufficiently accurate to make capitalization decisions has identified preferred domains of fab performance. This finding contradicts extant theory, which argues that all operating points on the same operating curve should reflect the same level of performance. The model is used to simulate the performance of a stylized fab that operates under realistic conditions. Results of the simulation show that significant additional revenue and profit can be generated by extending the lean approach to managing the operating curve that is practiced in most fabs today to an approach that is both lean and value driven. View full abstract»

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  • Scale, Scope, and Speed—Managing the Challenges of Multiproduct Manufacturing

    Page(s): 30 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (709 KB) |  | HTML iconHTML  

    An empirically grounded model characterizes the challenges of modern multiproduct manufacturing, where products that operate in highly contrasting economic environments run in one fab. Three product classes are taken into consideration-VLSI circuits for which unit sales prices are highly time dependent; specialty chips for which unit sales prices and total demand are specified a priori; and commodity components whose unit sales prices are low, predictable, and either flat or cyclical. The model calculates the impact of manufacturing cycle time on cost structure and the ability to generate revenue, and it simulates the economic consequences of a variety of production plans involving the three product classes. The findings of this paper suggest that an integrated approach to managing scale, scope, and fab cycle time can bring about dramatic increases in fab performance as measured by the net profit that the fab accumulates. View full abstract»

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  • The Potential for Economic Application of Maskless Lithography in Semiconductor Manufacturing

    Page(s): 39 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (745 KB) |  | HTML iconHTML  

    Maskless lithography has never played more than a niche role in semiconductor manufacturing, but with costs of masks for hard layers rising and the numbers of masks purchased over product lifetimes increasing, there is renewed interest today in maskless lithography. We assess the economics of production application of maskless lithography at the 45-nm technology node assuming the availability of a maskless lithography tool with various throughput capabilities. The analysis finds that selective and shrewd application of maskless lithography to layers with the most expensive masks and shortest mask lives would be economically attractive to many fabrication operations even for 300-mm maskless tool throughputs less than five wafers per hour. While a vendor of the desired maskless tools does not now exist, the business case for such a vendor is shown to be promising. View full abstract»

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  • Analysis of Wafer Sojourn Time in Dual-Arm Cluster Tools With Residency Time Constraint and Activity Time Variation

    Page(s): 53 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (478 KB) |  | HTML iconHTML  

    When scheduling cluster tools under wafer residency time constraints, wafer sojourn time in a processing module should be carefully controlled such that it is in a permissive range. Activity time variation often results in wafer sojourn time fluctuation and makes an originally feasible schedule infeasible. Thus, it is very important to know how the wafer sojourn time changes when activity time varies. With bounded activity time variation considered, this paper conducts a detailed analysis of wafer sojourn time variation in dual-arm cluster tools. To do so, a Petri net (PN) model and a real-time control policy are presented. Based on the PN model, real-time operational architecture, and real-time control policy, this paper analyzes the effect of activity time variation on wafer sojourn time delay at a process module and presents its upper bounds. The upper bounds are given in an analytical form and can be easily evaluated. With the wafer sojourn time analysis, it is possible to develop an effective method for schedulability analysis and optimal steady-state scheduling. An example is used to show the applications of the proposed approach. View full abstract»

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  • Localization and Electrical Characterization of Interconnect Open Defects

    Page(s): 65 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1516 KB) |  | HTML iconHTML  

    A technique for extracting the electrical and topological parameters of open defects in process monitor lines is presented. The procedure is based on frequency-domain measurements performed at both end points of the line. The location as well as the resistive value of the open defect are derived from attenuation and phase shift measurements. The characteristic defect-free impedance of the line and its propagation constant are considered to be unknowns, and their values are also derived from the above measurements. In this way, the impact of process parameter variations on the proposed model is diminished. The experimental setup required to perform the characterization measurements and a simple graphical procedure to determine the defect and line parameters are presented. Experimental results show a good agreement between the predicted location of the open and its real location, found by optical beam induced resistance change inspection. Errors smaller than 2% of the total length of the line have been observed in the experiments. View full abstract»

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  • Statistical Approach for Yield Optimization for Minimum Energy Operation in Subthreshold Circuits Considering Variability Issues

    Page(s): 77 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (599 KB) |  | HTML iconHTML  

    The supply voltage (V dd) and threshold voltage (V th) are two significant design variables that directly impact the performance and power consumption of circuits. The scaling of these voltages has become a popular option to satisfy performance and low power requirements. Subthreshold operation is a compelling approach for energy-constrained applications where processor speed is less important. However, subthreshold designs show dramatically increased sensitivity to process variations due to the exponential relationship of subthreshold drive current with V th variation and drastically growing leakage power. If there is uncertainty in the value of the threshold or supply voltage, the power advantages of this very low-voltage operation diminishes. This paper presents a statistical methodology for choosing the optimum V dd and V th under manufacturing uncertainties and different operating conditions to minimize energy for a given frequency in subthreshold operation while ensuring yield maximality. Unlike the traditional energy optimization, to find the optimal values for the voltages, we have considered the following factors to make the optimization technique more acceptable: the application-dependent design constraints, variations in the design variables due to manufacturing uncertainty, device sizing, activity factor of the circuit, and power reduction techniques. To maximize the yield, a two-level optimization is employed. First, the design metric is carefully chosen and deterministically optimized to the optimum point in the feasible region. At the second level, a tolerance box is moved over the design space to find the best location in order to maximize the yield. The feasible region, which is application dependent, is constrained by the minimum performance and the maximum ratio of leakage to total power in the V dd -V th plane. The center - - of the tolerance box provides the nominal design values for V dd and V th such that the design has a maximum immunity to the variations and maximizes the yield. The yield is estimated directly using the joint cumulative distribution function over the tolerance box requiring no numerical integration and saving considerable computational complexity for multidimensional problems. The optimal designs, verified by Monte Carlo and SPECTRE simulations, demonstrate significant increase in yield. By using this methodology, yield is found to be strongly dependent on the design metrics, circuit switching activity, transistor sizing, and the given constraints. View full abstract»

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  • Estimation and Control in Semiconductor Etch: Practice and Possibilities

    Page(s): 87 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB) |  | HTML iconHTML  

    Semiconductor wafer etching is, to a large extent, an open-loop process with little direct feedback control. Most silicon chip manufacturers rely on the rigorous adherence to a ??recipe?? for the various etch processes, which have been built up based on considerable historical experience. However, residue buildup and difficulties in achieving consistent preventative maintenance operations lead to drifts and step changes in process characteristics. This paper examines the particular technical difficulties encountered in achieving consistency in the etching of semiconductor wafers and documents the range of estimation and control techniques currently available to address these difficulties. An important feature of such an assessment is the range of measurement options available if closed-loop control is to be achieved. View full abstract»

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  • Semiconductor Manufacturing Process Monitoring Based on Adaptive Substatistical PCA

    Page(s): 99 - 108
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (631 KB) |  | HTML iconHTML  

    Increasing yield and improving product quality are two important issues in the area of semiconductor manufacturing. The purpose of multivariate statistical process control is to improve process operations by quickly detecting process abnormalities and diagnosing the sources of the detected process abnormalities. The statistical-based multiway principal component analysis (PCA) method has drawn increasing interest in semiconductor manufacturing process monitoring. However, there are several drawbacks of this method, including future value estimation, limited number of batches, and non-Gaussian behavior of the process data. This paper proposes a new adaptive substatistical PCA-based method that can avoid future value estimation. By employing support vector data description, a new monitoring statistic is developed that has no Gaussian limitation of the process data. In addition, correlations among the new method, multimodel, and multiway PCA are detailed. Capabilities of the proposed method are demonstrated by an industrial example. View full abstract»

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  • An Intelligent Run-to-Run Control Strategy for Chemical–Mechanical Polishing Processes

    Page(s): 109 - 120
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (633 KB) |  | HTML iconHTML  

    This paper presents a novel intelligent run-to-run control strategy for chemical-mechanical polishing (CMP) processes. With the help of the recursive least squares identification method for model building, a real-coded genetic algorithm is applied to adaptively adjust the discount coefficients for double exponentially weighted moving average (EWMA) controller. The online intelligent scheme can effectively prevent the CMP processes from reaching unstable condition and can thus achieve high control performance. To demonstrate the effectiveness and applicability of the proposed intelligent run-to-run control strategy, two typical case studies are worked out in this paper. Extensive simulation comparisons with traditional double EWMA run-to-run control were performed. The simulation results show that the proposed intelligent run-to-run control is able to achieve better control performance than conventional schemes, especially for a process that has nonlinearities, process noise, and extra large metrology delays. View full abstract»

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  • Pad Deflection-Based Model of Chemical–Mechanical Polishing for Use in CAD IC Layout

    Page(s): 121 - 131
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2547 KB) |  | HTML iconHTML  

    The use of chemical-mechanical polishing (CMP) during the integrated circuit (IC) fabrication process has allowed for the aggressive interconnect patterning that is necessary for modern microprocessor technology. However, as IC technology has moved into the deep submicron realm, nonidealities during polishing have begun to play a significant role in device yield and circuit performance. In order to accurately predict circuit performance, designers must consider the effects of CMP prior to fabrication. A physics-based model to predict feature-scale wear of devices during polishing is presented and integrated into a CAD framework to test the model on various IC layouts. The model is benchmarked against experimental data and shown to be qualitatively accurate in predicting surface topography evolution. View full abstract»

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  • Efficient Signal Transport Model for Remote Thermometry in Full-Scale Thermal Processing Systems

    Page(s): 132 - 140
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (534 KB) |  | HTML iconHTML  

    The rapid thermal processing of semiconductor devices is very temperature sensitive and requires precise temperature measurement. Light pipe radiation thermometers are widely used for temperature control during manufacturing by industry, and there is concern about errors associated with light pipe measurements. Modeling in simplified systems has helped in understanding the signal transport process in light pipes and errors associated with measurements in the past. Considering the small sensor area compared to the size of the semiconductor wafer and the remaining system components, modeling of the complete system has not been done due to the computational demand. A reverse Monte Carlo model can be used efficiently to model the signal transported to the photodetector in conjunction with a thermal model of the system to better characterize the system. The proposed method is demonstrated in a full-scale instrumented system with a light pipe thermometer, and the results are compared against previously published measurements from the system. View full abstract»

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  • Defect Detection of IC Wafer Based on Spectral Subtraction

    Page(s): 141 - 147
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1720 KB) |  | HTML iconHTML  

    In this paper, spectral subtraction is successfully applied to image processing and to detect defects in the integrated circuit (IC) image. By utilizing the characteristics of many of the same chips in a wafer, three images with defects located in the same position and different chips are obtained. The defect images contain the spectrum of standard image without any defects. Spectral subtraction presented in the paper can extract the standard image from the three defect images. The algorithm complexity of spectral subtraction detecting defects is close to that of Fourier transform. After obtaining the standard image, the speed and accuracy of defects detection can be greatly enhanced using the detection method presented in the paper. Using the image gray-scale matching technology, impact of illumination on IC defect detection is solved. Experiments demonstrate that spectral subtraction is fast and accurate to defect detection in an IC image, and the method has high robustness for illumination. View full abstract»

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  • 2010 IEEE International Reliability Physics Symposium (IRPS)

    Page(s): 148
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  • IEEE Transactions on Semiconductor Manufacturing information for authors

    Page(s): C3
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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721