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6th Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1965)

6-8 Oct. 1965

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  • [Front cover]

    Publication Year: 1965
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    Freely Available from IEEE
  • Table of contents

    Publication Year: 1965, Page(s):2 - 3
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    Freely Available from IEEE
  • Foreword

    Publication Year: 1965, Page(s): c3
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    Freely Available from IEEE
  • Threshold gate network synthesis

    Publication Year: 1965, Page(s):5 - 11
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (675 KB)

    A method of synthesizing networks of threshold gates is described. The method makes use of the solutions to the dual of a set of inequalities to guide the design. The procedure is suitable for a variety of network topologies, for multiple output networks, and for partially specified functions. The procedures described are suited to automatic computation. A program for performing logic design using... View full abstract»

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  • On maximum stability realizations of linearly separable Boolean functions

    Publication Year: 1965, Page(s):12 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1160 KB)

    This paper is concerned with the realization of linearly separable switching functions where the realization has maximum stability to coefficient and logical signal fluctuations. A realization algorithm is presented for sequentially selecting the coefficients where each coefficient is as small as possible given the values of the previously selected coefficients and the requirement that the realiza... View full abstract»

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  • Synthesis of counters with threshold elements

    Publication Year: 1965, Page(s):25 - 35
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1385 KB)

    The realization of a variety of counters with only one threshold gate per state variable and a minimum number of state variables is treated. Closed-form expressions are derived for the weights and thresholds for arbitrarily large scales. The resulting state assignments can be determined by simple algorithms, without recourse to analysis. View full abstract»

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  • Minimal linear decompositions of switching functions

    Publication Year: 1965, Page(s):36 - 40
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (755 KB)

    In view of the main objective of designing more efficient electronic computers, logical designers, in recent years, have been much interested in realization of switching functions by networks of threshold gates instead of the classical "AND" and "OR" gates. Naturally, it is desirable to obtain a most economic network which consists of the least number of threshold gates. This gives rise to the pro... View full abstract»

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  • Two-level threshold minimization

    Publication Year: 1965, Page(s):41 - 44
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (471 KB)

    In view of the main objective of designing more efficient electronic computers, logical designers, in recent years, have been much interested in realization of switching functions by networks of threshold gates instead of the classical "AND" and "OR" gates. Naturally, it is desirable to obtain a most economic network which consists of the least number of threshold gates. This gives rise to the pro... View full abstract»

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  • Cascade synthesis of finite-state machines

    Publication Year: 1965, Page(s):45 - 51
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (798 KB)

    One can construct any finite-state machine as a cascade interconnection of machines whose inputs either permute the states or reset them all to one state. Each permutation group needed in the construction is a homomorphic image of a group generated by the action of a set of input sequences on a state subset of the original machine. Proofs of these facts will be given and their application to the R... View full abstract»

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  • Decomposition of sequential machines

    Publication Year: 1965, Page(s):52 - 61
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1658 KB)

    This paper examines the problem of finding cascade decompositions for two or. more reduced sequential machines which have the same input, such that a common submachine may be factored out and serve as a predecessor machine feeding two or more successor machines which generate the outputs of the specified given machines. Necessary and sufficient conditions under which it is possible to obtain decom... View full abstract»

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  • Modular synthesis of sequential machines

    Publication Year: 1965, Page(s):62 - 70
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1177 KB)

    This paper discusses the synthesis of sequential machines with a class of specialized sequential building blocks. This class may be characterized as those sequential machines which have only a single memory element which is a function of external variables. General results are presented for the whole class and synthesis techniques are given for a specific type of module. View full abstract»

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  • On shift register realizations for sequential machines

    Publication Year: 1965, Page(s):71 - 83
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1633 KB)

    This paper considers the problem of determining whether a sequential machine, given by its flow table, can be realized in the form of binary shift registers. In general we are interested in a realization using the smallest number of shift registers possible. One-to-one assignments and many-to-one assignments are considered. Initially we use partitions for one-to-one assignments, then extend the me... View full abstract»

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  • On single-loop realizations of automata

    Publication Year: 1965, Page(s):84 - 93
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1377 KB)

    This paper is concerned with the problem of realizing a finite automaton A by a sequential circuit with a single feedback loop carrying a binary signal. To find such a realization, one must find a binary total-state partition, which can be used for feedback, for the flow table T of A or for some expanded Version of T. A method is presented for testing whether a given flow table possesses a feedbac... View full abstract»

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  • Feedback in asynchronous sequential circuits

    Publication Year: 1965, Page(s):94 - 104
    Cited by:  Papers (42)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1523 KB)

    In this paper we examine the problem of feedback in asynchronous sequential circuits. A procedure is presented whereby any normal fundamental mode flow table can be realized as a fundamental mode circuit with feedback index ⌈log2maxi(Si)⌉ where Si is the number of stable states in column i of the flow table and it is shown that this result is optimal. The realization requires no in... View full abstract»

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  • The synthesis of TANT networks

    Publication Year: 1965, Page(s):105 - 125
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2901 KB)

    This paper presents an algorithm for finding, for any given Boolean function, a least cost three-level AND-NOT network having uncomplemented inputs where the cost criterion is the number of gates. The approach taken is similar to the Quine-MeCluskey algorithm for two level AND/OR network synthesis. View full abstract»

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  • Reliability and fault-masking in n-variable NOR trees

    Publication Year: 1965, Page(s):126 - 142
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1491 KB)

    This paper presents an algorithm for finding, for any given Boolean function, a least cost three-level AND-NOT network having uncomplemented inputs where the cost criterion is the number of gates. The approach taken is similar to the Quine-MeCluskey algorithm for two level AND/OR network synthesis. View full abstract»

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  • Procedures for minimization of "Exclusive-or" and "Logical-equivalence" switching circuits

    Publication Year: 1965, Page(s):143 - 149
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (599 KB)

    The transformation which carries an arbitrary switching function represented by its disjunctive (or conjunctive) canonical form to its EXCLUSIVE-OR (Δ) (or the LOGICAL EQUIVALENCE (∇)) requiresmanipulation of vectors and square matrices of dimension 2n where n is the number of input variables. In this paper we develop a simple iterative procedure which gives the minimal Δ (or... View full abstract»

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  • A theory of high-speed clocked logic

    Publication Year: 1965, Page(s):150 - 161
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1409 KB)

    In this paper we concern Ourselves with the problem of obtaining high sequence rate sequential machines, machines which are constructed from realistic devices to operate at an input sequence rate which is independent of the machine complexity. To accomplish this result we have only to show a Construction to realize acceptably synchronous devices from badly timed, restricted fan-in and fan-out devi... View full abstract»

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  • A proof concerning infinite nets of logic elements without feedback

    Publication Year: 1965, Page(s):162 - 167
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (854 KB)

    Computers and other data processing equipments usually contain a basic pulse source (or clock) which keeps the various portions of the equipment in synchronization. When the size of the equipment increases significantly, however, or the clock frequency increases, the clock pulse can no longer be assumed to be at all portions of the hardware simultaneously and propagation delays for the clock pulse... View full abstract»

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  • Crossing sequences and off-line turing machine computations

    Publication Year: 1965, Page(s):168 - 172
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (787 KB)

    This paper is concerned with the computations performed by one-tape, off-line Turing machines. It introduces the idea of a "crossing sequence", and shows how such sequences can be used to analyze the behavior of off-line machines. It describes a class of recognition problems for which good estimates of computation time can be obtained by arguments based on the properties of crossing sequences. It ... View full abstract»

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  • Translational methods and computational complexity

    Publication Year: 1965, Page(s):173 - 178
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    This paper investigates the computational complexity of binary sequences as measured by the rapidity of their generation by multitape Turing machines. A "translational" method which escapes some of the limitations of earlier approaches leads to a refinement of the established hierarchy. The previous complexity classes are shown to possess certain translational properties. An related hierarchy of c... View full abstract»

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  • Hierarchies of memory limited computations

    Publication Year: 1965, Page(s):179 - 190
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1654 KB)

    This paper investigates the computational complexity of binary sequences as measured by the rapidity of their generation by multitape Turing machines. A "translational" method which escapes some of the limitations of earlier approaches leads to a refinement of the established hierarchy. The previous complexity classes are shown to possess certain translational properties. An related hierarchy of c... View full abstract»

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  • Memory bounds for recognition of context-free and context-sensitive languages

    Publication Year: 1965, Page(s):191 - 202
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1544 KB)

    This paper investigates the computational complexity of binary sequences as measured by the rapidity of their generation by multitape Turing machines. A "translational" method which escapes some of the limitations of earlier approaches leads to a refinement of the established hierarchy. The previous complexity classes are shown to possess certain translational properties. An related hierarchy of c... View full abstract»

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  • Deterministic context free languages

    Publication Year: 1965, Page(s):203 - 220
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1781 KB)

    A number of results about deterministic languages (languages accepted by pushdown automata with no choice of moves) are established. In particular, (1) each deterministic language is unambiguous. (2) the complement of each deterministic language is a deterministic language. (3) numerous operations which preserve deterministic languages (for example, intersection with a regular set) are obtained. (... View full abstract»

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  • On multi-head finite automata

    Publication Year: 1965, Page(s):221 - 228
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (817 KB)

    Let mn be the class of languages defined by n-head finite automata. The Boolean and Kleene closure properties of mn are investigated, and a relationship between mn and the class sets of n-tuples of tapes defined by n-tape finite automata is established. The relationships among the multi-head languages and the context-free and context-sensitive languages are investigated, and the adage, "Two heads ... View full abstract»

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