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IBM Journal of Research and Development

Issue 3 • Date May 1980

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Displaying Results 1 - 20 of 20
  • Preface

    Publication Year: 1980, Page(s): 267
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (106 KB)

    The progress in semiconductor memory technology over the past two decades is an excellent example of industrial synergism at its best. Semiconductor scientists and engineers, circuit and packaging technologists, and computer designers have contributed to the steady and phenomenal progress in semiconductor memory technology. View full abstract»

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  • A Silicon and Aluminum Dynamic Memory Technology

    Publication Year: 1980, Page(s):268 - 282
    Cited by:  Papers (13)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1301 KB)

    The Silicon and Aluminum Metal Oxide Semiconductor (SAMOS) technology is presented as a high-yield, low-cost process to make one-device-cell random access memories. The characteristics of the process are a multilayer dielectric gate insulator (oxide-nitride), a p-type polysilicon field shield, and a doped oxide diffusion source. Added yield-enhancing features are backside ion implant gettering, du... View full abstract»

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  • Cross-Coupled Charge-Transfer Sense Amplifier and Latch Sense Scheme for High-Density FET Memories

    Publication Year: 1980, Page(s):283 - 290
    Cited by:  Papers (5)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (569 KB)

    This paper describes a sense scheme for use on high-density one-device cell field effect transistor random access memories (FET RAMs). The high-sensitivity threshold-independent cross-coupled charge-transfer sense amplifier and latch is used. The IBM 64K-bit one-device dynamic memory cell FET RAM chip design is used as the vehicle for the discussion. Adaptations made on the sense amplifier and lat... View full abstract»

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  • Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement

    Publication Year: 1980, Page(s):291 - 298
    Cited by:  Papers (23)  |  Patents (16)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (587 KB)

    This paper describes the circuit schemes used to substitute redundant storage locations for defective ones found during testing. Word or bit lines are added along with appropriate bit steering circuitry to allow the replacement of a defective word or bit line. On-chip storage elements are “set” by the tester and used to store the binary addresses of the failing word or bit lines, whi... View full abstract»

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  • VLSI Device Phenomena in Dynamic Memory and Their Application to Technology Development and Device Design

    Publication Year: 1980, Page(s):299 - 309
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (893 KB)

    Ever-increasing density poses significant challenges to the device designer, who must relate an integrated technology to the numerous electrical characteristics required for successful memory design. Success of a VLSI technology depends as much on the extensive design of small devices as on the sophisticated lithography with which to fabricate them. Several dimensional limitations arise from the e... View full abstract»

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  • Reduction of Leakage by Implantation Gettering in VLSI Circuits

    Publication Year: 1980, Page(s):310 - 317
    Cited by:  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (832 KB)

    Damage introduced by ion implantation on the back side of the wafer is used to reduce the MOS transient (relaxation) and junction leakage; the technique is applied to dynamic memory cells. Conditions necessary to ensure efficient gettering by various species (B, Ar, Kr, and Xe) are established based on achieving a sufficient density of b = ½ 〈110〉 dislocations. When the implan... View full abstract»

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  • A 64K FET Dynamic Random Access Memory: Design Considerations and Description

    Publication Year: 1980, Page(s):318 - 327
    Cited by:  Papers (6)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (702 KB)

    The major design considerations and design features of an experimental 64K-bit random access memory (RAM), implemented in a double polysilicon gate technology, are described in this paper. Design tradeoffs addressing power supply selection and chip configuration alternatives are presented. This is followed by a description of the 8K-word by 8-bit FET dynamic RAM which uses single-transistor cells ... View full abstract»

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  • A 256K-Bit Charge-Coupled Device Memory

    Publication Year: 1980, Page(s):328 - 338
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (728 KB)

    This paper describes the design of an experimental 256K-bit serial-access memory using VLSI fabrication technology and low-power dynamic circuits. The memory array chip is implemented with a double polysilicon process and uses charge-coupled devices (CCDs) grouped in 64 blocks of 4K bits each. Operation is typically at a 300-ns-per-bit cycle for both read and write modes, with operating voltages o... View full abstract»

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  • A One-Device Memory Cell Using a Single Layer of Polysilicon and a Self-Registering Metal-to-Polysilicon Contact

    Publication Year: 1980, Page(s):339 - 347
    Cited by:  Papers (1)  |  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (672 KB)

    The fabrication and operation of a novel one-device dynamic memory cell are described. Like the conventional double overlapping polysilicon cell, the new memory cell has a diffused bit line and a metal word line, uses five basic masking operations, and provides essentially equivalent cell area for the same lithographic feature size. Unlike the double polysilicon cell, however, the new cell uses a ... View full abstract»

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  • Near-Ideal Si-SiO2 Interfaces

    Publication Year: 1980, Page(s):348 - 352
    Cited by:  Patents (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (420 KB)

    The Si-SiO2 interface plays a key role in insulated-gate field-effect transistors (IGFETs). Of principal concern are the interface charge density Qic and the fast-state density Nfs. These properties can be optimized by eliminating the transition region and creating an abrupt interface. Our work with the chemical vapor deposition (CVD) of SiO2 using a CO... View full abstract»

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  • Reliability of SiO2 Gate Dielectric with Semi-Recessed Oxide Isolation

    Publication Year: 1980, Page(s):353 - 361
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (630 KB)

    This paper reports the results of a study to minimize defects in the gate oxide and in the single crystal substrate of semi-recessed oxide (Semi-ROX) structures. It is shown that both an increase in oxidation mask thickness and a decrease in wet field oxidation temperature markedly reduce the incidence of low voltage breakdown in the gate oxide. Microscopic studies of samples which exhibited low v... View full abstract»

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  • Implanted Source/Drain Junctions for Polysilicon Gate Technologies

    Publication Year: 1980, Page(s):362 - 369
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (695 KB)

    Shallow (< 1.0-µm) n+-p junctions are required for dense dynamic FET memory. Ion implantation is a natural technology to fulfill the geometric requirements of shallow highly doped n+ regions in a dual polysilicon gate IGFET technology. However, implantation of 31P and 75As at high dose levels severely damages the crystal lattice and subseq... View full abstract»

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  • A Contactless Method for High-Sensitivity Measurement of p-n Junction Leakage

    Publication Year: 1980, Page(s):370 - 377
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (642 KB)

    A contactless p-n junction leakage measurement method is described that uses low-noise vhf oscillator circuitry to examine the dynamic memory-like behavior of the junctions. This method utilizes the eddy current loading effect, via inductive coupling, in order to determine the leakage-dependent decay time of the photoinduced voltage across the diffused p-n junctions. The contactless measurement is... View full abstract»

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  • 1/N Circuit and Device Technology

    Publication Year: 1980, Page(s):378 - 389
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (934 KB)

    The 1/N memory cell is the bipolar analog of the FET one-device cell. A thin dielectric and doped polysilicon are combined with bipolar technology to achieve a vertically integrated, high-density, fast-performance memory chip. The circuit design, device structure, and processing implementation for a 64K-bit dynamic, 1/N fractional-device, experimental bipolar memory are presented. Test results for... View full abstract»

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  • A System Solution to the Memory Soft Error Problem

    Publication Year: 1980, Page(s):390 - 397
    Cited by:  Papers (12)  |  Patents (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (638 KB)

    High-density and/or high-performance memory chip designs often create new reliability problems; one good example is the alpha-particle problem for high-density RAM and CCD chips, the problem being that soft errors may “line up” with existing hard errors, giving rise to double errors which are not correctable with conventionally implemented single-error-correcting double-error-detecti... View full abstract»

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  • Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product

    Publication Year: 1980, Page(s):398 - 409
    Cited by:  Papers (142)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (846 KB)

    A model with mixed Poisson statistics has been developed for calculating the yield for memory chips with redundant lines and for partially good product. The mixing process requires two parameters which are readily obtained from product data. The product is described in the model by critical areas which depend on the circuit's sensitivity to defects, and they can be determined in a systematic way. ... View full abstract»

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  • A Charge Injection Transistor Memory Cell

    Publication Year: 1980, Page(s):410 - 413
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (403 KB)

    In this paper, two versions of an experimental bipolar dynamic memory cell are described. The memory cell consists of one p-channel MOSFET and a bipolar npn transistor with extensive node sharing. The MOSFET device controls the charge injection into the floating base of the npn transistor, and the bipolar device provides amplification for the stored charge during read operation. For memories, this... View full abstract»

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  • Recent Papers by IBM Authors

    Publication Year: 1980, Page(s):414 - 417
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (386 KB)

    Reprints of the papers listed here may usually be obtained by writing directly to the authors. The authors' IBM divisions are identified as follows: CHQ is Corporate Headquarters; DPD, Data Processing Division; DSD, Data Systems Division; FED, Field Engineering Division; FSD, Federal Systems Division; GPD, General Products Division; GSD, General Systems Division; GTD, General Technology Division; ... View full abstract»

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  • Recent IBM Patents

    Publication Year: 1980, Page(s):418 - 419
    IEEE is not the copyright holder of this material | PDF file iconPDF (137 KB)
    Freely Available from IEEE
  • Authors

    Publication Year: 1980, Page(s):420 - 424
    IEEE is not the copyright holder of this material | PDF file iconPDF (528 KB)
    Freely Available from IEEE

Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

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Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center