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IBM Journal of Research and Development

Issue 4 • Date July 1982

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Displaying Results 1 - 16 of 16
  • Preface

    Page(s): 399 - 400
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    It is well known that a continuing trend in the development of digital computers has been towards improved cost efficiency, leading to expansion into new applications. In large measure this trend has resulted from continuing improvements in component technology. Remarkable advances in the miniaturization and integration of electronic components, particularly in the past ten years, have ushered in an era of microelectronics in which improvements of unprecedented magnitude in the size, cost, performance, and reliability of computer systems have been achieved. The emergence of microprocessor technology has played an especially significant role in this progress. View full abstract»

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  • Microprocessor Implementation of Mainframe Processors by Means of Architecture Partitioning

    Page(s): 401 - 412
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1208 KB)  

    The benefits of Large-Scale Integration (LSI) implementations have applied quite naturally to processors with relatively low performances and simple architectures; e.g., the one-chip microprocessors used in personal computers contain several thousand logic gates. Mainframe processors, however, have so far been limited to using logic chips that contain several hundred logic gates. The best use of LSI logic employs microprocessors to keep critical paths on chip, thus keeping pin counts and power dissipations within reasonable limits. Microprocessors have been extensively used to implement peripheral functions, such as I/O device control. However, as of this writing, a single state-of-the-art microprocessor cannot contain a mainframe processor function. Therefore, new machine organizations are needed to use today's state-of-the-art microprocessors to implement a mainframe processor. This paper examines several methods for applying LSI and microprocessors to the design of processors of increasing performance and complexity, and describes a number of specific approaches to microprocessor-based LSI implementation of System/370 processors. The most successful approaches partition the System/370 instruction set into subsets, each of which can be implemented by microcode on a special microprocessor or by programs written for an off-the-shelf microprocessor. View full abstract»

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  • A Microprocessor for Signal Processing, the RSP

    Page(s): 413 - 423
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1249 KB)  

    Signal processing is a data processing domain that contains a diversity of applications, including speech processing, image processing, radar, sonar, medical imaging, data communications, seismic processing, and many others. Despite the diversity of the applications, this processing domain has a very structured set of characteristics. These include real-time operation, dominance of arithmetic operations, and well-structured data flows. The Real-Time Signal Processor (RSP) is a microprocessor architecture that was created to exploit these characteristics in order to provide an expeditious and economical way to implement signal processing applications. In this paper, the organization and architecture of the RSP are described. Features of the RSP, such as the instruction pipeline and the fractional fixed-point arithmetic, which exploit the characteristics of signal processing to provide additional computational power, are emphasized. Other features, such as the powerful indexing, the saturation arithmetic, the guard bits, and the double-word-width accumulator, which add much to the processor's versatility and programmability, are also highlighted. The performance of the RSP is illustrated through examples. View full abstract»

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  • Rectangular Transforms for Digital Convolution on the Research Signal Processor

    Page(s): 424 - 430
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (759 KB)  

    The Rectangular Transform (RT) method for computing convolutions belongs to a family of Reduced Computational Complexity (RCC) algorithms. Convolution calculations by the RT method were programmed for the Research Signal Processor (RSP) and run on the RSP simulator, giving tabulations of numbers of RSP machine cycles. One of the original objectives was to see how well the original RSP architecture was suited to the RCC algorithms and to be able to make suggestions for possible changes. The results are also intended to demonstrate the efficiency of the RT convolution algorithms on a microprocessor with a limited instruction set and to show how to construct efficient RT programs for digital convolution. All results are given for the original RSP, as it was before the modification which resulted in the Real-time Signal Processor described in another paper in this issue. View full abstract»

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  • Real-Time Signal Processor Software Support

    Page(s): 431 - 439
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1209 KB)  

    The Real-Time Signal Processor (RSP) is a microprocessor optimized to provide fast, cost-efficient processing for signal processing applications. In order for the RSP to become fully useful, a complete set of software support tools needed to be developed. The hardware design and software development, which took place between 1978 and 1980, resulted in many architectural features which minimized hardware complexity at the expense of programmability. This paper describes the tools that were developed and the decisions that were involved, and includes hindsight comments on what was done. Particular emphasis is placed on the most interesting aspects of the software development, i.e., how the special architectural features of the RSP were handled to make the overall hardware/software system more programmable. View full abstract»

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  • Common Chip for Use in Disk and Diskette Controllers

    Page(s): 440 - 445
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (691 KB)  

    The advent of LSI technology makes common microprogrammable controllers very cost-effective today. This paper focuses on the application of microcontrollers for disk and diskette control functions and describes a custom-designed FET chip which is being developed for use in these types of controllers. The architecture, the functional organization, and the physical design of this chip are presented, and the requirement of matching a microcontroller to the application is discussed. View full abstract»

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  • Physical Design of a Custom 16-Bit Microprocessor

    Page(s): 446 - 453
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1040 KB)  

    The physical chip design aspects of a 16-bit, single-chip, custom-macro-designed microprocessor are described. This microprocessor represents the IBM System Products Division's highest-density VLSI FET processor design to date. The chip is a complex arrangement of over 6500 VLSI circuits utilizing a state-of-the-art polysilicon-gate HMOS-1 (high-performance MOS) technology. The physical design of this chip required the use of a comprehensive methodology, from conception through completion. The methodology used in the design of the microprocessor was based on a hierarchical approach and is presented in this paper. View full abstract»

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  • Design Considerations for a VLSI Microprocessor

    Page(s): 454 - 463
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1120 KB)  

    The machine architecture and design considerations for an interrupt-driven bipolar VLSI Microprocessor are presented. The processor is designed to a complex architecture and includes an integrated channel and a flexible storage interface. Floating-point functions are optional. A 3-ns custom bipolar technology was developed for the microprocessor, resulting in a very high circuit density package. The 50-mm four-chip air-cooled microprocessor module is packaged on a printed-circuit card with associated repowering circuits and high-speed random-access memory. Important design considerations and tradeoffs associated with the development of this machine, within specific cost, performance, reliability, and schedule objectives, are discussed. Various processor design techniques are described which minimize hardware where performance is not critical. A degree of functional parallelism is utilized, as well as timing flexibility, to attain the required performance. View full abstract»

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  • Bipolar Chip Design for a VLSI Microprocessor

    Page(s): 464 - 474
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1278 KB)  

    In this paper, a pseudo-custom approach to bipolar VLSI chip design is presented, and a hierarchical structure of logic macros assembled from building blocks is described. A strategy of placing the logic macros along with algorithmically designed PLA structures and ROS with a placement aid, and of wiring the placement with an automatic wiring program, is discussed. The paper also focuses on the implementation of this strategy in terms of technology, chip structure, and chip design methodology. In addition, chip statistics are presented and their implications are discussed. View full abstract»

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  • A VLSI Design Verification Strategy

    Page(s): 475 - 484
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1226 KB)  

    With the ever-increasing density, development cost, and turn-around time of VLSI chips it becomes increasingly important to have a design verification methodology which enables first-pass chips to be fully functional. The strategy discussed in this paper exploits the best attributes of the two traditional methods of design verification (i.e., software simulation and hardware modeling). Software simulation was chosen for its capability in the area of delay analysis and early functional checking. An automatically generated nodal-equivalent hardware model was built to provide the vehicle on which exhaustive functional checking could be performed. The model also operated as early user hardware on which functions such as operating systems, I/O adapters, and a floating-point feature could be tested. A technique known as interface emulation was used on certain well-defined subsystems to facilitate a shorter verification schedule through parallel debug efforts. View full abstract»

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  • A Bipolar VLSI Custom Macro Physical Design Verification Strategy

    Page(s): 485 - 496
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1172 KB)  

    The level of complexity and the turn-around time associated with the development of custom bipolar VLSI chips have defined the need for a highly structured physical and electrical design validation approach which can guarantee fully functional first-pass chips, yet be flexible enough to allow logical and physical designers the latitude necessary to achieve specified cost and performance objectives. This paper describes such a design verification strategy and its implied constraints on chip design. The rationale for comparing the logic equivalence of the high-level logical models to the low-level-device physical models is presented, a description of the hierarchical logical-to-physical and electrical checking is given, and its impact on cost and complexity is examined. View full abstract»

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  • Plant Automation in a Structured Distributed System Environment

    Page(s): 497 - 505
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1052 KB)  

    As VLSI technology evolves, miniaturization demands more sophisticated tools, instruments, and controls to manufacture the VLSI components. IBM's facility at East Fishkill, New York, has the responsibility for the development and manufacture of semiconductor products used in IBM data systems. This requires a sophisticated set of processes, inspections, and tests operating as a fully integrated system. In this paper, the design and implementation of a hierarchical distributed system for manufacturing control of integrated electronic components are described. The implementation includes distributed data bases and inter-level decoupling to ensure 24-hour manufacturing capabilities. Reasons for the choice of the processors used at various levels in the hierarchical network, and the communications required between them, are discussed. View full abstract»

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  • Construction of Bounded Delay Codes for Discrete Noiseless Channels

    Page(s): 506 - 514
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (978 KB)  

    Algorithms are described for constructing synchronous (fixed rate) codes for discrete noiseless channels where the constraints can be modeled by finite state machines. The methods yield two classes of codes with minimum delay or look-ahead. View full abstract»

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  • Recent Papers by IBM Authors

    Page(s): 515 - 520
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (698 KB)  

    Reprints of the papers listed here may usually be obtained by writing directly to the authors. The authors' IBM divisions or groups are identified as follows: CHQ is Corporate Headquarters; CPD, Communication Products Division; DSD, Data Systems Division; FED, Field Engineering Division; FSD, Federal Systems Division; GPD, General Products Division; GSD, General Systems Division; GTD, General Technology Division; IPD, Information Products Division; ISG, Information Systems Group; IS& CG, Information Systems & Communications Group; IS& TG, Information Systems & Technology Group; NAD, National Accounts Division; NMD, National Marketing Division; RES, Research Division; SPD, System Products Division; and SRI, Systems Research Institute. Journals are listed alphabetically by title; papers are listed sequentially for each journal. View full abstract»

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  • Recent IBM Patents

    Page(s): 521
    Save to Project icon | PDF file iconPDF (136 KB)  
    Freely Available from IEEE
  • Authors

    Page(s): 522 - 524
    Save to Project icon | PDF file iconPDF (459 KB)  
    Freely Available from IEEE

Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center