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IBM Journal of Research and Development

Issue 3 • Date May 1982

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Displaying Results 1 - 16 of 16
  • Preface

    Page(s): 276 - 277
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (349 KB)  

    Among computer designers the term “package” now generally implies all of the hardware used to provide physical support for and electrical interconnection of integrated circuit chips. Thus the computer package includes chip modules, cards, circuit boards, electrical connectors, cables, and frames. The design of a computer package involves both electrical and mechanical considerations, and package designers must also consider heat dissipation. The materials used in computer packages must meet a variety of physical, electrical, and environmental requirements, and the combinations of materials used strongly affect reliability. View full abstract»

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  • Cost/Performance Single-Chip Module

    Page(s): 278 - 285
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1185 KB)  

    The introduction of the high performance T2L device technology for the IBM 4300 Systems and the System/38 required extensions of the 24-mm metallized ceramic module used in prior IBM systems. The extension of the metallized ceramic technology into a physically larger 28-mm module, electrically enhanced with a reference plane and with fine line (0.025-mm) wiring, is described. The reliability of this module was evaluated with particular emphasis on corrosion and metal migration in humid environments and on exposure to atmospheric contaminants. View full abstract»

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  • The Thin-Film Module as a High-Performance Semiconductor Package

    Page(s): 286 - 296
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1258 KB)  

    This paper discusses a multichip module for future VLSI computer packages on which an array of silicon chips is directly attached and interconnected by high-density thin-film lossy transmission lines. Since the high-performance VLSI chips contain a large number of off-chip driver circuits which are allowed to switch simultaneously in operation, low-inductance on-module capacitors are found to be essential for stabilizing the on-module power supply. Novel on-module capacitor structures are therefore proposed, discussed, and evaluated. Material systems and processing techniques for both the thin-film interconnection lines and the capacitor structures are also briefly discussed in the paper. Development of novel defect detection and repair techniques has been identified as essential for fabricating the Thin-Film Module with practical yields. View full abstract»

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  • Advanced Printed-Circuit Board Design for High-Performance Computer Applications

    Page(s): 297 - 305
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1027 KB)  

    A new integrated circuit packaging structure was needed to support the new 90-mm multilayer ceramic modules, known as Thermal Conduction Modules (TCMs), used in the IBM 3081 computers. The structure developed eliminates one level of packaging (the card level) and allows up to nine TCMs to be plugged directly into a large multilayer printed-circuit board using a new zero-insertion-force connector system. The board has 18 internal circuit planes for signal and power distribution and accommodates new signal cabling, power bus, terminating resistors, decoupling capacitors, and cooling hardware, forming a packaged unit of up to a quarter million logic gates and half a million bits of memory. This paper focuses on the detailed design of the printed-circuit board and on its signal and power transmission characteristics. View full abstract»

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  • High-Density Board Fabrication Techniques

    Page(s): 306 - 317
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1569 KB)  

    A variety of construction methods can be used to form high-density printed-circuit boards. The electrical and mechanical requirements of a design strongly influence the choice of processes used to produce the finished product. The introduction of physically large high-density boards required the development of many new processes, several of which are critical to the electrical performance of the composite. In this paper the process sequence employed in the fabrication of the 3081 high-density board is described, with particular emphasis on the selection of the critical processes used in its manufacture. The 3081 registration system is also discussed, and a new method for merging through-hole location data with the data representing the location of the conducting layers is presented. View full abstract»

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  • Development of Interconnection Technology for Large-Scale Integrated Circuits

    Page(s): 318 - 327
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1009 KB)  

    The size, cost, reliability, and serviceability of modern large data processing systems are influenced by the electrical interconnections required among the hundreds or thousands of chips they contain. The development of the complex interconnection design scheme is profoundly influenced by the interactions among the component and subassembly designs: modules, printed-circuit boards, cables, connectors, etc. The design scheme is also strongly affected by the constraints imposed by manufacturing process limitations and by environmental factors, such as cooling and corrosion. This paper deals with these interactions and constraints as encountered in the interconnection design of the IBM 3081 system and the design discipline required to deal with them. View full abstract»

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  • Influence on LSI Package Wireability of Via Availability and Wiring Track Accessibility

    Page(s): 328 - 341
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1420 KB)  

    In this paper, experiments are reported which use automatic global and line-packing wiring routines, supplemented by a restricted maze runner, to evaluate the overall influences of several important physical variables upon the wireability of several logic-circuit package types. The logic circuits are contained in subpackages (e.g., modules carrying chips), which are inserted, using pins, into the carrier package in a regular array of holes otherwise available as vias interconnecting the wiring planes. Over a range of connection counts from several hundred to several thousand, it is found that “overflows” (connections not wired by the program) amounting to as much as 10 or 15% of the wires can be substantially reduced in number by careful design. This can be done by using a sufficient number of programmable vias (greater than one per used pin) and by using a track grid ensuring maximum global track accessibility to all pins, or by a combination of both of these tactics in conjunction with suitable wiring algorithms. Some simple theoretical arguments are given which characterize the design problem in the light of the results. View full abstract»

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  • Lead Reduction Among Combinatorial Logic Circuits

    Page(s): 342 - 348
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (625 KB)  

    The paper provides a description of the behavior of lead reduction among combinatorial logic circuits. Methods by which one may design the lead reduction architecture for modular packaging schemes are developed. The methods are then applied to the design of the lead reduction architecture of an integrated circuit chip and a nine-chip cell. View full abstract»

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  • Electrical Design of a High Speed Computer Package

    Page(s): 349 - 361
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1416 KB)  

    A methodology for optimizing the design of an electrical packaging system for a high speed computer is described. The pertinent parameters are first defined and their sensitivities are derived so that the proper design trade-offs can ultimately be made. From this procedure, a set of rules is generated for driving a computer aided design system. Finally, there is a discussion of design optimization and circuit and package effects on machine performance. View full abstract»

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  • A VLSI Bipolar Metallization Design with Three-Level Wiring and Area Array Solder Connections

    Page(s): 362 - 371
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1700 KB)  

    The ability to interconnect large numbers of integrated silicon devices on a single chip has been greatly aided by a three-level wiring capability and large numbers of solderable input/output terminals on the face of the chip. This paper describes the design and process used to fabricate the interconnections on IBM's most advanced bipolar devices. Among the subjects discussed are thin film metallurgy and contacts, e-beam lithography and associated resist technology, a high temperature lift-off stencil for metal pattern definition, planarized rf sputtered SiO2 insulation/passivation, the “zero-overlap” via hole innovation, in situ rf sputter cleaning of vias prior to metallization, and area array solder terminals. View full abstract»

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  • Optimization of Indium-Lead Alloys for Controlled Collapse Chip Connection Application

    Page(s): 372 - 378
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1096 KB)  

    Indium-lead solders are used for IBM controlled collapse chip connections (C-4s) to improve fatigue life in temperature cycling for large chip applications. Using 50% In-Pb alloy, which is expensive, has posed a number of manufacturing and reliability concerns. This paper presents the results of development studies leading to the use of a low-indium solder alloy for C-4 applications. This alloy overcomes all previous concerns while exceeding the fatigue life specification of the high-indium alloy. Also described are the variables and tests used to evaluate C-4 performance of In-Pb alloys over the 5% to 50% range. Results are presented graphically and mathematically to show the improvement obtained with indium-content solders over the conventional tin-lean alloys. View full abstract»

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  • Immersion Wave Soldering Process

    Page(s): 379 - 382
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (389 KB)  

    Immersion wave soldering is a new technique for soldering advanced printed circuit boards. In this process, an assembled and fixtured printed circuit board is immersed in a fluxing fluid and preheated to the soldering temperature. The fluxing fluid is glycerine activated with ethylenediamine tetra-acetic acid (EDTA). After preheating and while still immersed in the fluxing fluid, the fixtured board is passed over a tin-bismuth eutectic (42% Sn, 58% Bi) solder wave. This technique has several advantages over conventional soldering processes, including elimination of solder dross formation, improved control over solder deposition, reduced thermal shock, easier cleaning after soldering, and improved flux effectiveness. View full abstract»

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  • Recent Papers by IBM Authors

    Page(s): 383 - 387
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (590 KB)  

    Reprints of the papers listed here may usually be obtained by writing directly to the authors. The authors' IBM divisions or groups are identified as follows: CHQ is Corporate Headquarters; CPD, Communication Products Division; DSD, Data System Divsision; FED, Field Engineering Division; FSD, Federal Systems Division; GSD, General Systems Division; GTD, General Technology Division; IPD, Information Products Division; ISG, Information Systems Group; IS&CG, Information Systems & Communications Group; IS& TG, Information Systems & Technology Group; NAD, National Accounts Division; NMD, National Marketing Division; RES, Research Division; SPD, System Products Division; and SRI, Systems Research Institute. Journals are listed alphabetically by title; papers are listed sequentially for each journal. View full abstract»

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  • Recent IBM Patents

    Page(s): 388 - 390
    Save to Project icon | PDF file iconPDF (340 KB)  
    Freely Available from IEEE
  • Authors

    Page(s): 391 - 395
    Save to Project icon | PDF file iconPDF (694 KB)  
    Freely Available from IEEE
  • Errata [Erratum]

    Page(s): 396
    Save to Project icon | PDF file iconPDF (65 KB)  
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Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center