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IBM Journal of Research and Development

Issue 2 • Date March 1984

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Displaying Results 1 - 14 of 14
  • Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review

    Publication Year: 1984, Page(s):124 - 134
    Cited by:  Papers (165)  |  Patents (40)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (842 KB)

    This paper presents a state-of-the-art review of error-correcting codes for computer semiconductor memory applications. The construction of four classes of error-correcting codes appropriate for semiconductor memory designs is described, and for each class of codes the number of check bits required for commonly used data lengths is provided. The implementation aspects of error correction and error... View full abstract»

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  • Table of Contents

    Publication Year: 1984, Page(s): 125
    IEEE is not the copyright holder of this material | PDF file iconPDF (92 KB)
    Freely Available from IEEE
  • An Introduction to Arithmetic Coding

    Publication Year: 1984, Page(s):135 - 149
    Cited by:  Papers (131)  |  Patents (75)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1157 KB)

    Arithmetic coding is a data compression technique that encodes data (the data string) by creating a code string which represents a fractional value on the number line between 0 and 1. The coding algorithm is symbolwise recursive; i.e., it operates upon and encodes (decodes) one data symbol per iteration or recursion. On each recursion, the algorithm successively partitions an interval of the numbe... View full abstract»

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  • A Universal Reed-Solomon Decoder

    Publication Year: 1984, Page(s):150 - 158
    Cited by:  Papers (24)  |  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (637 KB)

    Two architectures for universal Reed-Solomon decoders are given. These decoders, called time-domain decoders, work directly on the raw data word as received without the usual syndrome calculation or power-sum-symmetric functions. Up to the limitations of the working registers, the decoders can decode any Reed-Solomon codeword or BCH codeword in the presence of both errors and erasures. Provision i... View full abstract»

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  • Implementation and Evaluation of a (b,k)-Adjacent Error-Correcting/Detecting Scheme for Supercomputer Systems

    Publication Year: 1984, Page(s):159 - 169
    Cited by:  Papers (1)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (964 KB)

    This paper describes a coding scheme developed for a specific supercomputer architecture and structure. The code considered is a shortened (b,k)-adjacent single-error-correcting double-error probabilistic-detecting code with b=5, k=1, and code group width = 4. An evaluation of the probabilistic double-error-detection capability of the code was performed for different organizations of the coding/de... View full abstract»

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  • Fault Alignment Exclusion for Memory Using Address Permutation

    Publication Year: 1984, Page(s):170 - 176
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (580 KB)

    A significant improvement in memory fault tolerance, beyond what is already provided by the use of an appropriate error-correcting code (ECC), can be achieved by electronic chip swapping, without any compromise of data integrity as large numbers of faults are allowed to accumulate. Since most large and medium-sized semiconductor memories are organized so that each bit position of the system word (... View full abstract»

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  • Fault-Tolerant Design Techniques for Semiconductor Memory Applications

    Publication Year: 1984, Page(s):177 - 183
    Cited by:  Papers (13)  |  Patents (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (609 KB)

    Advances in semiconductor memory technology towards higher-density and higher-performance memory chips have created new reliability challenges for the memory system designer. An example would be the multiple-bit-per-chip organization with the chip outputs used in the same word. This design structure would be prone to uncorrectable errors with conventionally implemented single-error-correcting doub... View full abstract»

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  • Fault-Tolerant Memory Simulator

    Publication Year: 1984, Page(s):184 - 195
    Cited by:  Papers (7)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (920 KB)

    Memory systems in modern computers employ a variety of methods to achieve fault tolerance, such as single- or double-error correction, page deallocation, or the use of spare chips or cells. Such methods ensure that the failure rate of the system is considerably less than the sum of the failure rates of the components. However, these methods also complicate the task of evaluating system reliability... View full abstract»

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  • A General-Purpose Memory Reliability Simulator

    Publication Year: 1984, Page(s):196 - 205
    Cited by:  Papers (7)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (820 KB)

    With rapid advances in computer memory capacity and performance, coupled with corresponding increases in the expense of field service calls, memory reliability and optimal maintenance strategies have become more and more important in terms of customer satisfaction and field service cost. At the same time, significant improvements in error correction and recovery over recent years have made the pre... View full abstract»

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  • Analysis of Correctable Errors in the IBM 3380 Disk File

    Publication Year: 1984, Page(s):206 - 211
    Cited by:  Papers (29)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (568 KB)

    A method of analyzing the correctable errors in disk files is presented. It allows one to infer the most probable error in the encoded-data stream given only the unencoded readback and error-correction information. This method is applied to the errors observed in seven months of operation of four IBM 3380 head-disk assemblies. It is shown that nearly all the observed errors can be explained as sin... View full abstract»

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  • Iterative Exhaustive Pattern Generation for Logic Testing

    Publication Year: 1984, Page(s):212 - 219
    Cited by:  Papers (18)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (615 KB)

    Exhaustive pattern logic testing schemes provide all possible input patterns with respect to an output in the set of test patterns. This paper is concerned with the problem that arises when this is to be done simultaneously with respect to a number of outputs, using a single test set. More specifically, in this paper we describe an iterative procedure for generating a test set consisting of n-dime... View full abstract»

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  • Recent Papers by IBM Authors

    Publication Year: 1984, Page(s):220 - 225
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (507 KB)

    Reprints of the papers listed here may usually be obtained by writing directly to the authors. The authors' IBM divisions or groups are identified as follows: CHQ is Corporate Headquarters; CPD, Communication Products Division; DSD, Data Systems Division; FED, Field Engineering Division: FSD, Federal Systems Division; GPD, General Products Division; GSD, General Systems Division; GTD, General Tech... View full abstract»

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  • Recent Books by IBM Authors

    Publication Year: 1984, Page(s): 226
    IEEE is not the copyright holder of this material | PDF file iconPDF (97 KB)
    Freely Available from IEEE
  • Recent IBM Patents

    Publication Year: 1984, Page(s):227 - 230
    IEEE is not the copyright holder of this material | PDF file iconPDF (234 KB)
    Freely Available from IEEE

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The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

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Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center