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IBM Journal of Research and Development

Issue 5 • Date Sept. 1984

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Displaying Results 1 - 17 of 17
  • A software architecture for a mature design automation system

    Publication Year: 1984 , Page(s): 501 - 511
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1123 KB)  

    Design automation systems are groups of programs used to aid the design of the electronic portions of computers. IBM has used such systems for over twenty-five years, and has a large number of experienced users who place severe requirements upon their design automation system. The essential requirement is that design programs must be easy to use in the way that a particular development location wi... View full abstract»

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  • A device-independent graphics package for CAD applications

    Publication Year: 1984 , Page(s): 512 - 523
    Cited by:  Patents (3)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1323 KB)  

    GSSP (Graphics Support Subroutine Package) is a device-independent two-dimensional graphics package developed by Engineering Design Systems (EDS) to support several major electronic and mechanical computer-aided design applications within IBM. Graphics systems supported range from interactive, high-function, distributed-graphics workstations to passive graphic-output devices. GSSP provides many of... View full abstract»

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  • An interactive system for VLSI chip physical design

    Publication Year: 1984 , Page(s): 524 - 536
    Cited by:  Papers (12)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (2138 KB)  

    The Federal Systems Division has developed a structured design methodology and a companion chip physical design system that has been used to build seven large VLSI chips (ranging in size from 7K to 36K logic primitives). Using the MVISA system, a logic designer has complete control and responsibility for the total chip design. Our experience has been that when this highly interactive software and ... View full abstract»

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  • LSS: A system for production logic synthesis

    Publication Year: 1984 , Page(s): 537 - 545
    Cited by:  Papers (85)  |  Patents (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1146 KB)  

    For some time we have been exploring methods of transforming functional specifications into hardware implementations that are suitable for production. The complexity of this task and the potential value have continued to grow with the increasing complexity of processor design and the mounting pressure to shorten machine design times. This paper describes the evolution of the Logic Synthesis System... View full abstract»

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  • Automated technology mapping

    Publication Year: 1984 , Page(s): 546 - 556
    Cited by:  Papers (6)  |  Patents (3)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1189 KB)  

    Logic “mapping,” or “transformation,” refers to the process of converting a logic design from one form of specification to another. The output is usually a specific technology implementation and the input could range from a previous technology implementation to a high-level design language. Motivated initially by the problem of test case generation for new technologies,... View full abstract»

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  • Hardware design and description languages in IBM

    Publication Year: 1984 , Page(s): 557 - 563
    Cited by:  Papers (11)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (653 KB)  

    Hardware design languages (HDLs) allow computer hardware to be described in sufficient detail to be simulated and built, such a description being at a sufficiently high level of abstraction to make the complete design readily intelligible to anyone skilled in that language. A number of HDLs have been developed and are in use in IBM. To date, no overwhelming case can be made for choosing any one HD... View full abstract»

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  • Using a hardware simulation engine for custom MOS structured designs

    Publication Year: 1984 , Page(s): 564 - 571
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1039 KB)  

    Mixed-level simulation techniques are widely used in VLSI designs for verification and test evaluation. In this paper we indicate how to perform mixed-level simulation on structured MOS designs using the Yorktown Simulation Engine (YSE), a hardware simulator developed at IBM. On the YSE, simulation can be done at the functional, gate, and transistor levels. The design specification used by the YSE... View full abstract»

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  • PSI: A symbolic layout system

    Publication Year: 1984 , Page(s): 572 - 580
    Cited by:  Papers (7)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (671 KB)  

    A symbolic layout tool, PSI, is described for use with IBM circuit technology. Significant features of PSI are used with multiple circuit technologies, adaptation to rapid changes of technology design rules, creation of nested designs, and extensive designer control over the spacing process. View full abstract»

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  • Constraint solver for generalized IC layout

    Publication Year: 1984 , Page(s): 581 - 589
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1049 KB)  

    This paper presents a constraint solver suitable for use in a general symbolic IC layout system. The essential features of the constraint solver, which is intended to place few restrictions on the source of the constraints to be solved, are that it accommodate mixed equality and inequality constraints, that it allow selective “maximization” of variables, that it proceed with any numb... View full abstract»

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  • Custom Chip/Card Design System

    Publication Year: 1984 , Page(s): 590 - 595
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (600 KB)  

    The Custom Chip/Card Design System (CCDS) is a set of software applications, tied together via a common data interchange, that is used for the design, analysis, and checking of custom electronic circuits. CCDS is intended to unite the separate electrical, logical, and physical design phases into a single design process. The underlying principle of the system rests on the idea of describing the pro... View full abstract»

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  • ACORN: A system for CVS macro design by tree placement and tree customization

    Publication Year: 1984 , Page(s): 596 - 602
    Cited by:  Papers (4)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1092 KB)  

    ACORN is a system for the physical design of cascode voltage switch (CVS) macros which utilizes tree placement and tree customization to improve macro wirability. The results obtained by designing a 43-tree differential (DCVS) macro on a masterslice chip image are presented to illustrate the design improvements. In this example, tree placement reduces wire length and via count by 12 percent relati... View full abstract»

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  • KWIRE: A multiple-technology, user-reconfigurable wiring tool for VLSI

    Publication Year: 1984 , Page(s): 603 - 612
    Cited by:  Papers (9)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1582 KB)  

    In a VLSI design environment where a range of chip technologies are available and concurrent chip designs are commonplace, it is not feasible to build a wiring program for each technology. Additionally, a chip's design methodology may demand specific abilities from a wiring program. KWIRE was developed to meet the needs of a multiple-technology, multiple-methodology VLSI design community. It has b... View full abstract»

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  • An iterative-improvement penalty-function-driven wire routing system

    Publication Year: 1984 , Page(s): 613 - 624
    Cited by:  Papers (22)  |  Patents (9)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1250 KB)  

    A wire routing system (VIKING) has been developed for interconnection packages. It uses iterative-improvement methods that allow “illegalities” (such as wire crossings within a plane) at intermediate stages of the routing, eliminates some drawbacks of conventional sequential routers, and extends the range of penalty functions with respect to which a wiring configuration can be optimi... View full abstract»

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  • A CMOS LSSD test generation system

    Publication Year: 1984 , Page(s): 625 - 635
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1010 KB)  

    Automatic test pattern generators based on the stuck-fault concept are theoretically inadequate in their ability to generate test patterns for CMOS circuits. A new set of pin faults, called CMOS faults, is discussed that can represent the necessary test pattern sequences for these circuits. Processing of these faults by a new test pattern generator, called the Enhanced Test Generator (ETG), is als... View full abstract»

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  • Yield model for fault clusters within integrated circuits

    Publication Year: 1984 , Page(s): 636 - 640
    Cited by:  Papers (21)  |  Patents (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (364 KB)  

    Generalized negative binomial statistics turns out to be a model of the fault distribution in very large chips or wafers with internal defect clusters. This is expected to influence large chip and full wafer redundancy requirements. Furthermore, the yield appears to be affected by an experimental dependence of the average number of faults on chip area. View full abstract»

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  • Recent papers by IBM authors

    Publication Year: 1984 , Page(s): 641 - 648
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (646 KB)  

    Reprints of the papers listed here may usually be obtained by writing directly to the authors. The authors' IBM divisions or groups are identified as follows: CHQ is Corporate Headquarters; CPD. Communication Products Division; DSD, Data Systems Division; FED, Field Engineering Division; FSD, Federal Systems Division; GPD, General Products Division; GTD, General Technology Division; IPD, Informati... View full abstract»

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  • Recent IBM patents

    Publication Year: 1984 , Page(s): 649 - 650
    Save to Project icon | PDF file iconPDF (178 KB)  
    Freely Available from IEEE

Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center