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IBM Journal of Research and Development

Issue 5.6 • Date Sept. 1991

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Displaying Results 1 - 22 of 22
  • Preface

    Publication Year: 1991, Page(s):571 - 572
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (176 KB)

    Computer systems have traditionally been designed with the goal of maximizing the use of the central processing unit (CPU) foremost in the minds of the architects. This approach has resulted from the great expense of designing and building this component of computer systems. Over the years, the trend has been to construct larger and more expensive CPUs, to provide hardware and software constructs ... View full abstract»

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  • The IBM Victor V256 partitionable multiprocessor

    Publication Year: 1991, Page(s):573 - 590
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1634 KB)

    Victor V256 is a partitionable message-passing multiprocessor with 256 processors, designed and in use at the IBM Thomas J. Watson Research Center. Our goals are to explore computer architectures based on the message-passing model and to use these architectures to solve real applications. We present the architecture of the Victor system, particularly its partitioning and nonintrusive monitoring. W... View full abstract»

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  • Design choices for the TOP-1 multiprocessor workstation

    Publication Year: 1991, Page(s):591 - 602
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (962 KB)

    A snoopy-cache-based multiprocessor workstation called TOP-1 (TOkyo research Parallel processor-1) was developed to evaluate multiprocessor architecture design choices as well as to conduct research on operating systems, compilers, and applications for multiprocessor workstations. TOP-1 is a ten-way multiprocessor using the Intel 80386™ microprocessor chip and the Weitek WTL 1167™ fl... View full abstract»

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  • Hierarchically interconnected multiprocessors

    Publication Year: 1991, Page(s):603 - 616
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1486 KB)

    The design of interconnection networks is a central problem in parallel computing, especially for shared-memory systems, where network latency, or delay, is one factor that limits system size. This paper discusses aspects of one particular approach to network structure, a design comprising a multiplicity of subnetworks that form a hierarchy of paths. The hierarchy includes fast paths that are used... View full abstract»

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  • Operating system support for parallel programming on RP3

    Publication Year: 1991, Page(s):617 - 634
    Cited by:  Papers (3)  |  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1621 KB)

    RP3, the Research Parallel Processing Prototype, was a research vehicle for exploring the hardware and software aspects of highly parallel computation. RP3 was a shared-memory machine that was designed to be scalable to 512 processors; a 64-processor machine was in operation from October 1988 through March 1991. A parallel-programming environment based on the Mach operating system was developed, a... View full abstract»

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  • The RP3 program visualization environment

    Publication Year: 1991, Page(s):635 - 651
    Cited by:  Papers (8)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1994 KB)

    The performance promised for parallel systems often proves to be somewhat elusive. This paper discusses one important technique for improving the performance of parallel software: program visualization—helping programmers visualize the real behavior of an application or system by presenting its state and progress in a continuous graphic fashion. An environment for visualization of program e... View full abstract»

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  • The Parallel Processing Compute Server

    Publication Year: 1991, Page(s):653 - 666
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1337 KB)

    The Parallel Processing Compute Server (PPCS) is a distributed-memory multiprocessing system consisting of System/370™ microprocessors (33 at present) interconnected through a matrix switch. This paper describes the hardware configuration, the extensions to the System/370 instruction set that are provided to support the distributed memory and interprocessor signaling, the modifications to t... View full abstract»

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  • Clustering IBM Enterprise System/3090 computers for parallel execution of FORTRAN programs

    Publication Year: 1991, Page(s):667 - 679
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1225 KB)

    Two IBM Enterprise System/3090™ Model 600J computer systems, each with six processors capable of executing vector and scalar instructions, have been connected into a cluster for parallel execution of single FORTRAN programs. The clustering is achieved through a combination of software and hardware. When enabled for parallel execution and allowed to use all twelve processors in the cluster, ... View full abstract»

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  • Exploiting database parallelism in a message-passing multiprocessor

    Publication Year: 1991, Page(s):681 - 695
    Cited by:  Papers (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1354 KB)

    Parallel processing may well be the only means of satisfying the long-term performance requirements for database systems: an increase in throughput for transactions and a drastic decrease in response time for complex queries. In this paper, we review various alternatives, and then focus entirely on exploiting parallel-processing configurations in which general-purpose processors communicate only v... View full abstract»

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  • Multiplication of a symmetric banded matrix by a vector on a vector multiprocessor computer

    Publication Year: 1991, Page(s):697 - 706
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (998 KB)

    This paper describes how to vectorize and parallelize the multiplication of a symmetric banded matrix by a vector, on a vector multiprocessor. The ideas presented involve two packed-band-storage schemes, and implementations for both schemes are studied. The best among the uniprocessor solutions proposed achieves a maximum of 37.1 Mflops on an IBM Enterprise System/3090™ 400E with Vector Fac... View full abstract»

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  • Waveform-relaxation-based circuit simulation on the Victor V256 parallel processor

    Publication Year: 1991, Page(s):707 - 720
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1217 KB)

    Present-day circuit-analysis tools permit designers to verify performance for circuits consisting of up to 10,000 transistors. However, current designs often exceed several tens of thousands and even hundreds of thousands of transistors. The gap between the number of transistors that can be simulated and the number per design inhibits proper analysis prior to manufacturing, yet incomplete analysis... View full abstract»

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  • Further results using the overhead model for parallel systems

    Publication Year: 1991, Page(s):721 - 726
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (490 KB)

    A performance model that takes into consideration the overhead incurred in the use of a parallel system is used to show that the maximum value of the speedup achieved by the parallel system for a fixed problem may be much smaller than the number of processors required to achieve that value. It is also shown that under certain conditions, the problem size may be varied so as to achieve a speedup cl... View full abstract»

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  • The parallel C (pC) programming language

    Publication Year: 1991, Page(s):727 - 741
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1344 KB)

    We describe pC (parallel C), an extension of the ANSI C programming language to support medium- to large-grain parallel programming in both shared- and distributed-memory environments. pC aims to make programming for parallel processors accessible to the C community by enriching the C programming model with a small set of constructs supporting parallelism. pC supports shared- and distributed-memor... View full abstract»

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  • Low-overhead scheduling of nested parallelism

    Publication Year: 1991, Page(s):743 - 765
    Cited by:  Papers (11)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1980 KB)

    Nested parallelism has the potential not only to permit more parallelism than non-nested parallelism, but to result in better load balancing. However, nested parallelism will not be profitable unless the overhead of scheduling nested parallel constructs can be made nonprohibitive. Previous implementations of nested parallel constructs have been fairly expensive and therefore have not been able to ... View full abstract»

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  • Execution of automatically parallelized APL programs on RP3

    Publication Year: 1991, Page(s):767 - 777
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (960 KB)

    We have implemented an experimental APL/C compiler, which accepts ordinary APL programs and produces C programs. We have also implemented a run-time environment that supports the parallel execution of these C programs on the RP3 computer, a shared-memory, 64-way MIMD machine built at the IBM Thomas J. Watson Research Center. The APL/C compiler uses the front end of the APL/370 compiler and imposes... View full abstract»

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  • Automatic partitioning of a program dependence graph into parallel tasks

    Publication Year: 1991, Page(s):779 - 804
    Cited by:  Papers (26)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (4128 KB)

    In this paper, we describe a general interprocedural framework for partitioning a program dependence graph into parallel tasks for execution on a multiprocessor system. Partitioning techniques are necessary to execute a parallel program at the appropriate granularity for a given target multiprocessor. The problem is to determine the best trade-off between parallelism and overhead. It is desirable ... View full abstract»

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  • Monitoring the performance of commercial T1-rate transmission service

    Publication Year: 1991, Page(s):805 - 814
    Cited by:  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (924 KB)

    This paper gathers the scattered empirical and theoretical elements of the performance-management problem for commercial T1-rate transmission service and integrates these elements in a useful way. We propose two variants of a time-based performance-monitoring algorithm that are insensitive to the arrival pattern of transmission errors. The first variant compares a count of errored seconds accumula... View full abstract»

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  • A trace-driven study of CMS file references

    Publication Year: 1991, Page(s):815 - 828
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1271 KB)

    This paper presents a detailed study of file reference patterns by users of a VM/CMS interactive system. The data were collected from two different IBM locations via CMON, a CMS monitoring facility. We present background information about the CMS file system, the CMON program, and our data-reduction programs, as well as a discussion of the results. Some earlier studies of this type have been restr... View full abstract»

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  • Recent publications by IBM authors

    Publication Year: 1991, Page(s):829 - 848
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1585 KB)

    The information listed here is supplied by the Institute for Scientific Information and other outside sources. Reprints of the papers may be obtained by writing directly to the first author cited. Information on books may be obtained by writing to the publisher. Journals and books are listed alphabetically by title; papers are listed sequentially for each journal. View full abstract»

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  • Recent IBM patents

    Publication Year: 1991, Page(s):849 - 853
    IEEE is not the copyright holder of this material | PDF file iconPDF (354 KB)
    Freely Available from IEEE
  • Author index for papers Volume 35

    Publication Year: 1991, Page(s):854 - 857
    IEEE is not the copyright holder of this material | PDF file iconPDF (250 KB)
    Freely Available from IEEE
  • Subject index for papers in Volume 35

    Publication Year: 1991, Page(s):858 - 862
    IEEE is not the copyright holder of this material | PDF file iconPDF (347 KB)
    Freely Available from IEEE

Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

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Meet Our Editors

Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center