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IBM Journal of Research and Development

Issue 5 • Date Sept. 1994

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Displaying Results 1 - 14 of 14
  • Preface

    Publication Year: 1994, Page(s):490 - 491
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (172 KB)

    During the four years since the RISC System/6000® (RS/6000) announcement in February of 1990, IBM® has strengthened its product line with microprocessor enhancements, increased memory capacity, improved graphics, greatly expanded I/O adapters, and new AIX® and compiler releases. In 1991, IBM began planning for future RS/6000 systems that would span the range from small, batter... View full abstract»

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  • POWER2: Next generation of the RISC System/6000 family

    Publication Year: 1994, Page(s):493 - 502
    Cited by:  Papers (12)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (837 KB)

    Since its announcement, the IBM RISC System/6000® processor has characterized the aggressive instruction-level parallelism approach to achieving performance. Recent enhancements to the architecture and implementation provide greater superscalar capability. This paper describes the architectural extensions which improve storage reference bandwidth, allow hardware square-root computation, and... View full abstract»

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  • POWER2 fixed-point, data cache, and storage control units

    Publication Year: 1994, Page(s):503 - 524
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1602 KB)

    The POWER2™ fixed-point, data cache, and storage control units provide a tightly integrated subunit for a second-generation high-performance superscalar RISC processor. These functional units provide dual fixed-point execution units and a large multiported data cache, as well as high-performance interfaces to memory, I/O, and the other execution units in the processor. These units provide t... View full abstract»

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  • POWER2 floating-point unit: Architecture and implementation

    Publication Year: 1994, Page(s):525 - 536
    Cited by:  Papers (6)  |  Patents (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (939 KB)

    The POWER2™ floating-point unit (FPU) extends the concept of the innovative multiply-add fused (MAF) ALU of the RISC System/6000® processor to provide a floating-point unit that sets new standards, not only for computation capability but for data throughput and processor flexibility. The POWER2 FPU achieves a performance (MFLOPS) rate never accomplished before by a personal workstati... View full abstract»

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  • POWER2 instruction cache unit

    Publication Year: 1994, Page(s):537 - 544
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (648 KB)

    This paper describes the instruction cache unit (ICU) of the IBM POWER2™ processor, with emphasis on improvements over the original POWER ICU design. The POWER2 ICU incorporates a new compare-branch scheme that minimizes processing time penalties, a second branch processor, increased branch look-ahead capability, and doubled instruction-fetch and instruction- dispatch bandwidth. View full abstract»

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  • The POWER2 performance monitor

    Publication Year: 1994, Page(s):545 - 554
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (771 KB)

    The POWER2™ performance monitor (“monitor”) provides the detailed hardware measurements necessary to study the hardware/software interactions of workloads executed by the POWER2 processor. The monitor is integrated into the processor and is fully software accessible. Of interest is the ability of this monitor to selectively measure specific software processes with minimal pert... View full abstract»

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  • Commercial workload performance in the IBM POWER2 RISC System/6000 processor

    Publication Year: 1994, Page(s):555 - 561
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (565 KB)

    We describe features of the POWER2™ processor and memory subsystem that enhance RISC System/6000® performance of commercial workloads. We explain the performance characteristics of commercial workloads and some of the common benchmarks used to measure them. Our own analysis methods are also described. View full abstract»

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  • Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms

    Publication Year: 1994, Page(s):563 - 576
    Cited by:  Papers (4)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1098 KB)

    We describe the algorithms and architecture approach to produce high-performance codes for numerically intensive computations. In this approach, for a given computation, we design algorithms so that they perform optimally when run on a target machine—in this case, the new POWER2™ machines from the RS/6000 family of RISC processors. The algorithmic features that we emphasize are funct... View full abstract»

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  • Instruction scheduling in the TOBEY compiler

    Publication Year: 1994, Page(s):577 - 593
    Cited by:  Papers (1)  |  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1278 KB)

    The high performance of pipelined, superscalar processors such as the POWER2™ and PowerPC™ is achieved in large part through the parallel execution of instructions. This fine-grain parallelism cannot always be achieved by the processor alone, but relies to some extent on the ordering of the instructions in a program. This dependence implies that optimizing compilers for these process... View full abstract»

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  • Trace-directed program restructuring for AIX executables

    Publication Year: 1994, Page(s):595 - 603
    Cited by:  Papers (5)  |  Patents (24)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (809 KB)

    This paper presents the design and implementation of trace- directed program restructuring (TDPR) for AIX® executable programs. TDPR is the process of reordering the instructions in an executable program, using an actual execution profile (or instruction address trace) for a selected workload, to improve utilization of the existing hardware architecture. Generally, the application of TDPR r... View full abstract»

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  • Design considerations for the PowerPC 601 microprocessor

    Publication Year: 1994, Page(s):605 - 620
    Cited by:  Papers (1)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1385 KB)

    The PowerPC 601™ microprocessor (601) is the first member of a family of processors that support IBM's PowerPC Architecture™. The 601 is a general-purpose processor based on a superscalar design point. As with any development effort, the 601 development program had several different, often conflicting, design goals. The most important requirements were support for the PowerPC Archite... View full abstract»

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  • Implementation of the PowerPC 601 microprocessor

    Publication Year: 1994, Page(s):621 - 632
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1004 KB)

    To produce a marketable PowerPC™ microprocessor on a short development schedule, the logic had to be designed in a manner flexible enough to allow quick modifications without sacrificing high performance and density when customized cells were required. This was accomplished for the PowerPC 601™ microprocessor (601) with a high-level design-language description, which was synthesized ... View full abstract»

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  • Recent publications by IBM authors

    Publication Year: 1994, Page(s):633 - 639
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (586 KB)

    The information listed here is supplied by the Institute for Scientific Information and other outside sources. Complete addresses are provided for the lead author of each publication. Journals and books are listed alphabetically by title; papers are listed sequentially for each journal. View full abstract»

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  • Recent IBM patents

    Publication Year: 1994, Page(s):641 - 648
    IEEE is not the copyright holder of this material | PDF file iconPDF (560 KB)
    Freely Available from IEEE

Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

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Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center