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IBM Journal of Research and Development

Issue 1.2 • Date Jan. 1995

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Displaying Results 1 - 23 of 23
  • Preface

    Page(s): 3
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    Within the past decade CMOS has become the technology of choice for a broad range of semiconductor products. High-density DRAMs, high-speed processors, and low-power devices for mobile applications are key examples. Underlying this widespread appeal are the distinguishing advantages that CMOS provides: an exceptionally low power-delay product, the ability to accommodate millions of devices on a single chip, and flexible, custom design methodologies which permit optimization, as required, for lowest cost, lowest power, or highest speed. View full abstract»

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  • Editor's note

    Page(s): 3
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    Freely Available from IEEE
  • Design at the system level with VLSI CMOS

    Page(s): 5 - 22
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1523 KB)  

    This paper explores high-performance central processing unit (CPU) design with VLSI CMOS. Workstations are the focus, because they were first to apply the synergism of CMOS, VLSI, and reduced-instruction-set computing (RISC). But the advances of CMOS now encompass all computing system design, and extend to newly created environments. We discuss CMOS extendibility in the highest-performance areas. View full abstract»

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  • Interconnect design with VLSI CMOS

    Page(s): 23 - 31
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (781 KB)  

    Historically, high-performance logic circuit interchip design has focused on bipolar emitter-coupled logic (ECL) circuits and signals, but VLSI CMOS has attained performance levels at which problems unique to its characteristics must be addressed for design optimization. In this paper, CMOS interchip circuit models are applied to develop packaging and wiring constraints for synchronous communication. View full abstract»

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  • Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

    Page(s): 33 - 42
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (916 KB)  

    An experimental 2.0-volt low-power PowerPC 601™ Microprocessor built in a modified 3.6-volt, 0.6-µm IBM CMOS technology is described. By using unmodified tasks from the 3.6-volt design, a 3× power savings was realized while maintaining nearly the original performance. The use of selective scaling provides high performance at reduced power supply voltage. This technique, applicable to selected existing product designs, may allow early entry into the low-power market while minimizing new process development expense. The technique proposes hyperscaled reductions in specific electrical and physical parameters, while keeping horizontal layout rules unchanged. Static chip designs, which comprise the majority of 601 circuitry, respond well to the alterations. In addition, potential reliability detractors are deuced or eliminated. Challenges to this technique include I/O interfacing and minimizing leakages associated with low device thresholds. The 601 design and its base technology are described, a long with the experimental changes. The paper reviews the motivation behind low-power microprocessor development, alternative power-saving techniques being practiced, and opportunities for continued power reduction. View full abstract»

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  • A 64Kb × 32 DRAM for graphics applications

    Page(s): 43 - 50
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (767 KB)  

    A high-speed 2Mb CMOS DRAM with 32 data I/Os is described. A 0.6-µm CMOS process with a single polysilicon layer, two levels of metal, and substrate-plate trench-capacitor (SPT) memory cells is used to fabricate the chip. It is designed to provide the wide data bandwidth required by high-performance graphics applications. A 35-ns access time with an 80-ns cycle time has been demonstrated. The 32-bit data bus and the high-speed feature achieve more than two times better graphics performance than conventional dual-port memories. A sensing method with a 2/3 VDD bit-line precharge voltage and a limited bit-line voltage swing is exploited to optimize speed and power. The chip, which operates on a 5-V power supply, dissipates 140 mA at the 80-ns cycle time. View full abstract»

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  • Multipurpose DRAM architecture for optimal power, performance, and product flexibility

    Page(s): 51 - 62
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1007 KB)  

    An 18Mb DRAM has been designed in a 3.3-V, 0.5-µm CMOS process. The array consists of four independent, self-contained 4.5Mb quadrants. The chip output configuration defaults to 1Mb × 18 for optimization of wafer screen tests, while 3.3-V or 5.0-V operation is selected by choosing one of two M2 configurations. Selection of 2Mb × 9 or 1Mb × 18 operation with the various address options, in extended data-out or fast-page mode, is accomplished by selective wire-bonding during module build. Laser fuses enable yield enhancement by substituting eight 512Kb array I/O slices for nine in each quadrant of the 18Mb array. This substitution is independent in each quadrant and results in 1Mb × 16 operation with 2Mb × 8, 4 Mb × 4, and 4Mb × 4 with any 4Mb independently selectable (4Mb × 4 w/4 CE). Input and control circuitry are designed such that performance margins are constant across output and functional configurations. The architecture also provides for “cut-downs” to 16Mb, 4.5Mb, and 4Mb chips with I/O and function as above. View full abstract»

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  • Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier

    Page(s): 63 - 72
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (999 KB)  

    To be competitive with copper technology for links and bus applications, optoelectronics must be made affordable. One means of achieving a low-cost optoelectronics link is to adapt volume-manufactured components. This may imply CMOS optoelectronic integrated circuits (OEICs), which are suggested by the huge CMOS IC volumes being produced for computer logic and memory, and red laser diodes, which are already in demand for the consumer and storage markets. In this paper, we demonstrate a potential low-cost link using a monolithically integrated Si photodiode and CMOS preamplifier, a multimode fiber-optic transmission medium, and red, vertical-cavity surface-emitting lasers (VCSELs). The integrated receiver shows a 3.5-dB improvement in received power when light at 670 nm instead of 845 nm is used; it operates error free at both the Fibre Channel rate of 531.25 Mb/s and the SONET OC-12 rate of 622.08 Mb/s. The red VCSELs are shown to be capable of a 1.5-Gb/s transmission data rate with as little as 18 mW average power dissipation. The potential for fabricating arrays using both of these technologies for optical buses is discussed. View full abstract»

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  • CMOS circuits for Gb/s serial data communication

    Page(s): 73 - 81
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (866 KB)  

    The functional characteristics and design challenges associated with a variety of communication-related circuits are presented. These include the mixed-signal design and noise issues associated with high-speed clock generation and recovery for serial data communication. Hardware results are presented on the noise properties of common integrated voltage-controlled oscillator (VCO) circuits. View full abstract»

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  • Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications

    Page(s): 83 - 91
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (915 KB)  

    The design challenges and custom design techniques associated with low-power, small-area, high-performance CMOS digital signal-processing circuits for hard-disk-drive applications are presented. The advantages of custom design are demonstrated by an example custom digital FIR filter macro that provides substantial improvement in performance, area, and power dissipation over standard-cell implementations. View full abstract»

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  • Digital delay line clock shapers and multipliers

    Page(s): 93 - 103
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1008 KB)  

    Two digital techniques have been developed to generate an internal clock signal from an external reference clock supplied to a microprocessor. The first method constitutes a clock shaper circuit that produces an output clock that has a 50% duty cycle regardless of the duty cycle of the input reference clock. The second technique generates an internal clock that is an N/2 multiple of the frequency of the input clock, where N is an integer greater than 1. Both methods are entirely digital and are independent of process and temperature variations. Their accuracy limits are determined by the technology. Both circuits are described and their results compared. View full abstract»

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  • A low-noise TTL-compatible CMOS off-chip driver circuit

    Page(s): 105 - 112
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (691 KB)  

    Low-noise TTL-compatible off-chip driver (OCD) circuits are very important, especially for low-power electronics, but scaled-down CMOS technology requires a lower operating voltage of 3.3 V, while most applications require 5 V. The dual power-supply requirement makes the design of OCD challenging, first because pull-up devices, especially p-MOS devices, must be able to handle an off-chip voltage of 5.6 V, which is higher than an on-chip VDD of 2.8 V, and second because pull-down devices should be able to discharge a capacitive load of 5.6 V while operating at a minimum on-chip VDD of 2.8 V. This extreme difference in operating voltage makes the circuits susceptible to ringing and performance degradation due to hot-electron effects. In this paper, we describe a low-noise OCD which has been successfully used in IBM second-generation 4Mb low-power DRAM (LPDRAM) and in other products. For pull-ups, two stacked p-MOS devices with floating n-wells are used, but they are operated in different modes dependi ng on the supply voltage. The pull-down devices are basically composed of two stages, one of which is in the diode configuration with its gate and drain shorted together during the pull-down. Detailed circuit designs to achieve low noise while meeting the performance requirements are described. View full abstract»

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  • Architectural timing verification of CMOS RISC processors

    Page(s): 113 - 129
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1442 KB)  

    We consider the problem of verification and testing of architectural timing models ("timers") coded to predict cycles-per-instruction (CPI) performance of advanced CMOS superscalar (RISC) processors. Such timers are used for pre-hardware performance analysis and prediction. As such, these software models play a vital role in processor performance tuning as well as application-based competitive analysis, years before actual product availability. One of the key problems facing a designer, modeler, or application analyst who uses such a tool is to understand how accurate the model is, in terms of the actual design. In contrast to functional simulators, there is no direct way of testing timers in the classical sense, since the “correct” execution time (in cycles) of a program on the machine model under test is not directly known or computable from equations, truth tables, or other formal specifications. Ultimate validation (or invalidation) of such models can be achieved under actual hardware availability, by direct comparisons against measured performance. However, deferring validation solely to that stage would do little to achieve the overall purpose of accurate pre-hardware analysis, tuning, and projection. We describe a multilevel validation method which has been used successfully to transform evolving timers into highly accurate pre-hardware models. In this paper, we focus primarily on the following aspects of the methodology: a) establishment of cause-effect relationships in terms of model defects and the associated fault signatures; b) derivation of application-based test loop kernels to verify steady-state (periodic) behavior of pipeline flow, against analytically predicted signatures; and c) derivation of synthetic test cases to verify the “core” parameters characterizing the pipeline-level machine organization as implemented in the timer model. The basic tenets of the theory and its application are described in the co- - ntext of an example processor, comparable in complexity to an advanced member of the PowerPC™ 6XX processor family. View full abstract»

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  • High-level synthesis in an industrial environment

    Page(s): 131 - 148
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1548 KB)  

    The use of modern hardware-description languages in the chip design process has allowed designs to be modeled at higher abstraction levels. More powerful modeling styles, such as register-transfer and behavioral level specifications, have spurred the development of high-level synthesis techniques in both industry and academia. However, despite the many research efforts, the technology is not yet in widespread use in industry. This paper presents the IBM High-Level Synthesis System (HIS), which is the first such system to be used in production in IBM. HIS synthesizes gate-level networks from VHDL models at various levels of abstraction. The main algorithms, modeling capabilities, and methodology considerations in the HIS system are presented. Results show that HIS is capable of producing implementations comparable to or better than those of the existing methodology, while shortening the design time significantly. The HIS system is currently in production use and evaluation in several IBM sites for processors and peripheral chip designs, as well as being an external commercial product. View full abstract»

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  • Verity—A formal verification program for custom CMOS circuits

    Page(s): 149 - 165
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1399 KB)  

    In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of current-generation processors and the necessity for manual designer intervention throughout the design process, proving design correctness is a major concern. In this paper we discuss Verity, a formal verification program for symbolically proving the equivalence between a high-level design specification and MOS transistor-level implementation. Verity applies efficient logic comparison techniques which implicitly exercise the behavior for all possible input patterns. For a given register-transfer level (RTL) system model, which is commonly used in present-day methodologies, Verity validates the transistor implementation with respect to functional simulation and verification performed at the RTL level. View full abstract»

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  • The evolution of IBM CMOS DRAM technology

    Page(s): 167 - 188
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1971 KB)  

    The development of DRAM at IBM produced many novel processes and sophisticated analysis methods. Improvements in lithography and innovative process features reduced the cell size by a factor of 18.8 in the time between the 4Mb and 256Mb generations. The original substrate plate trench cell used in the 4Mb chip is still the basis of the 256Mb technology being developed today. This paper describes some of the more important and interesting innovations introduced in IBM CMOS DRAMs. Among them, shallow-trench isolation, I-line and deep-UV (DUV) lithography, titanium salicidation, tungsten stud contacts, retrograde n-well, and planarized back-end-of-line (BEOL) technology are core elements of current state-of-the-art logic technology described in other papers in this issue. The DRAM specific features described are borderless contacts, the trench capacitor, trench-isolated cell devices, and the “strap.” Finally, the methods for study and control of leakage mechanisms which degrade DRAM retention time are described. View full abstract»

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  • Overview of gate linewidth control in the manufacture of CMOS logic chips

    Page(s): 189 - 200
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1085 KB)  

    This paper is an overview of the methods used at the Burlington facility of the IBM Microelectronics Division to improve channel-length tolerance control in the manufacture of CMOS logic chips. We cover aspects of 1) the impact of channel-length control on chip performance, yield, and reliability; 2) our use of an electrical linewidth monitor which permits high-volume, accurate measurements to quantify polysilicon gate linewidth variability and its improvements; and 3) our efforts to reduce photolithographic and etching contributions to the linewidth variability. View full abstract»

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  • Integrated cost and productivity learning in CMOS semiconductor manufacturing

    Page(s): 201 - 213
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1036 KB)  

    This paper describes a cost and productivity learning process that was carried out on a large-capacity CMOS manufacturing line at the IBM Burlington facility from 1991 to 1993. Major productivity gains were realized through process and tool improvements affecting yield, and through work-in-progress optimization and scrap reduction. Significant cost learning was also accomplished through tool cost management, capital depreciation and space cost reductions, and manpower optimization. View full abstract»

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  • A half-micron CMOS logic generation

    Page(s): 215 - 227
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1255 KB)  

    During the early 1990s, half-micron lithography was demonstrated in 16Mb DRAM fabrication. Utilization of this capability for CMOS logic devices within IBM followed with a trio of programs, each with different performance, density, feature list, and schedule. The first version melded 3.3/3.6-V 16Mb DRAM MOSFET devices with an improved version of an existing dense, planar, reliable multilevel back-end-of-line (BEOL) metallization and wiring technology. Since it was built directly from existing technologies, it was released quite quickly. A 3.3-V follow-on technology was added several months later. This logic offering added a local interconnect and a faster device. A second follow-on achieved greater speed improvement, calling upon a 2.5-V power supply and very tight channel-length control to obtain performances 50% above previous-generation standards, at lower power. View full abstract»

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  • CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications

    Page(s): 229 - 244
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1477 KB)  

    Deep-submicron CMOS is the primary technology for ULSI systems. Currently, the state-of-the-art CMOS device has a 0.25-µm effective channel length and operates at 2.5 V. As the CMOS technology is extended into the deep submicron range, it is estimated that the next generation will have a nominal channel length of 0.15 µm with a supply voltage of ≤2 V. In this paper, two potential technologies with application to 1.X-V CMOS are presented. First, a bulk CMOS technology with the nominal channel length of 0.15 µm is described. It is next argued that because of issues related to power dissipation, such a device may face problems when operated at its maximum speed-density potential in high-performance logic chips. CMOS on a silicon-on-insulator (SOI) substrate offers circuits with lower power at the same performance. Such a CMOS technology, with channel lengths down to less than 0.1 µm, is described next. This technology is particularly useful for applications near a 1.0-V supply. We describe, for example, a 512Kb SRAM with an access time of less than 3.5 ns at 1.X V. The clear power-performance advantage of CMOS on SOI over that of CMOS on bulk silicon in the 1.X-V regime makes it the technology of choice for sub-0.25-µm CMOS generations. View full abstract»

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  • CMOS scaling into the 21st century: 0.1 µm and beyond

    Page(s): 245 - 260
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1458 KB)  

    This paper describes the design, fabrication, and characterization of 0.1-µm-channel CMOS devices with dual n+/p+ polysilicon gates on 35-A gate oxide. A 2× performance gain over 2.5-V, 0.25-µm CMOS technology is achieved at a power supply voltage of 1.5 V. In addition, a 20× reduction in active power/circuit is obtained at a supply voltage of < 1 V with the same delay as the 0.25-micron CMOS. These results demonstrate the feasibility of high-performance and low-power room-temperature 0.1-µm CMOS technology. Beyond 0.1 µm, a number of fundamental device and technology issues must be examined: oxide and silicon tunneling, random dopant distribution, threshold voltage nonscaling, and interconnect delays. Several alternative device structures (in particular, low-temperature CMOS and double-gate MOSFET) for exploring the outermost limit of silicon scaling are discussed. View full abstract»

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  • Recent publications by IBM authors

    Page(s): 261 - 273
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1035 KB)  

    The information listed here is supplied by the Institute for Scientific Information and other outside sources. Complete addresses are provided for the lead author of each publication. Journals and books are listed alphabetically by title; papers are listed sequentially for each journal. View full abstract»

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  • Recent IBM patents

    Page(s): 275 - 280
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    Freely Available from IEEE

Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center