By Topic

IBM Journal of Research and Development

Issue 6 • Date Nov. 1996

Filter Results

Displaying Results 1 - 9 of 9
  • Serial Storage Architecture

    Page(s): 591 - 602
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (919 KB)  

    This paper describes Serial Storage Architecture (SSA), a definition and general specification of a high-performance serial link for the attachment of input/output devices. An overview is given of the architecture itself, followed by a general description of the hardware implementation of a dual-port SSA node on a single chip. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A fast, highly reliable data compression chip and algorithm for storage systems

    Page(s): 603 - 613
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (934 KB)  

    Data compression allows more efficient use of storage media and communication bandwidth, and standard compression offerings for tape storage have been well established since the late 1980s. Compression technology lowers the cost of storage without changing applications or data access methods. The desire to extend these cost/performance benefits to higher-data-rate media and broader media forms, such as DASD storage subsystems, motivated the design and development of the IBMLZ1 compression algorithm and its implementing technology. The IBMLZ1 compression algorithm was designed not only for robust and highly efficient compression, but also for extremely high reliability. Because compression removes redundancy in the source, the compressed data become extremely vulnerable to data corruption. Key design objectives for the IBMLZ1 development team were efficient hardware execution, efficient use of silicon technology, and minimum system-integration overhead. Through new observations of pattern matching, match-length distribution, and the use of graph vertex coloring for evaluating data flows, the IBMLZ1 compression algorithm and the chip family achieved the above objectives. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The past and present roles of computer-aided engineering in DASD design

    Page(s): 615 - 621
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (583 KB)  

    At the heart of today's computer-aided engineering (CAE) revolution is finite element modeling (FEM). This paper presents a brief history of how FEM simulations interact with and have significant impact on the design process of storage devices. The discussion is limited to structural static and dynamic effects on head/disk assemblies (HDAs) and components. FEM is integral to the design process; it is primarily a predictive/diagnostic design tool that provides engineers with detailed information on the performance of a design. FEM is most effective during the concept phase, where it can sort out many performance issues before the design parameters are constrained. Also, FEM can help to optimize critical structures within the system. As a diagnostic tool, FEM supplements testing by predicting in advance the properties and behavior of the device. A three-piece suspension design is presented as an example of how FEM and design work in harmony. An FEM of the entire structure was built to verify design and to fine-tune dimensions. Areas that required reinforcement and frequencies that seemed too low were identified, and the structure was modified. This process was repeated several times until the design satisfied the requirements. In addition to the suspension design example, a thermal deformation problem with a 3.5-in. actuator comb assembly is discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Architectural verification of advanced storage controllers

    Page(s): 623 - 630
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (571 KB)  

    The architectural complexity of advanced storage controllers has increased to a point at which architectural verification methods based on document inspections and reviews are no longer effective. To facilitate the architectural verification process, a high-performance simulator (TurboSim) has been developed for architectural-level verification. The TurboSim application includes a set of architectural-level models, which represent essential architectural components, and an automatic test case generator (ATG). The TurboSim ATG is used to generate realistic representations of customer direct access storage device (DASD) track data. The track data are used to drive different TurboSim simulation scenarios. After demonstrating its effectiveness as an architectural verification tool, TurboSim was enhanced to support the automatic generation of hardware test cases. These hardware test cases are used to ensure that the hardware implementation matches architectural specifications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Charge-metering sampling circuits and their applications

    Page(s): 631 - 640
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    Charge-metering sampling circuits comprise a new CMOS circuit class for sampled analog data applications. They avoid some drawbacks of conventional sampling circuits without the use of operational amplifiers. They lightly load their inputs, may be cascaded without buffering to provide analog pipelining, and avoid charge injection errors. Application to linear and nonlinear digital-to-analog converters (DACs), particularly for active matrix display data line drivers, is detailed. In the display application, the nonlinear charge-metering DACs provide a predetermined nonlinear relationship between digital input and display luminance down to the least significant bit, avoiding compromising color reproduction by the use of a piecewise-linear response. Experimental verification of this new circuit class has included the design and fabrication of a cross section of an integrated CMOS six-bit digital-analog data line driver. Experimental results are presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Recent publications by IBM authors

    Page(s): 641 - 649
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    The information listed here is supplied by the Institute for Scientific Information and other outside sources. Reprints of the papers may be obtained by writing directly to the first author cited. Journals are listed alphabetically by title; papers are listed sequentially for each journal. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Recent IBM patents

    Page(s): 651 - 672
    Save to Project icon | PDF file iconPDF (1327 KB)  
    Freely Available from IEEE
  • Author index for papers in Volume 40

    Page(s): 673 - 676
    Save to Project icon | PDF file iconPDF (245 KB)  
    Freely Available from IEEE
  • Subject index for papers in Volume 40

    Page(s): 677 - 682
    Save to Project icon | PDF file iconPDF (339 KB)  
    Freely Available from IEEE

Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center