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IBM Journal of Research and Development

Issue 3 • Date May 1997

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Displaying Results 1 - 12 of 12
  • Preface

    Publication Year: 1997, Page(s):203 - 204
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (244 KB)

    This issue of the IBM Journal of Research and Development contains papers selected from those presented at the 1996 Workshop on Performance Analysis and Its Impact on Design (PAID-96). This workshop was held March 27–29, 1996, at the IBM Austin Research Laboratory, and was sponsored by the IBM Research Division as one of the technical events organized to mark the 50th anniversary of IBM Res... View full abstract»

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  • Performance analysis on a CC-NUMA prototype

    Publication Year: 1997, Page(s):205 - 214
    Cited by:  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1052 KB)

    Cache-coherent nonuniform memory access (CC-NUMA) machines have been shown to be a promising paradigm for exploiting distributed execution. CC-NUMA systems can provide performance typically associated with parallel machines, without the high cost associated with parallel programming. This is because a single image of memory is provided on a CC-NUMA machine. Past research on CC-NUMA machines has fo... View full abstract»

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  • Understanding some simple processor-performance limits

    Publication Year: 1997, Page(s):215 - 232
    Cited by:  Papers (15)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1664 KB)

    To understand processor performance, it is essential to use metrics that are intuitive, and it is essential to be familiar with a few aspects of a simple scalar pipeline before attempting to understand more complex structures. This paper shows that cycles per instruction (CPI) is a simple dot product of event frequencies and event penalties, and that it is far more intuitive than its more popular ... View full abstract»

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  • Automatic selection of high-order transformations in the IBM XL FORTRAN compilers

    Publication Year: 1997, Page(s):233 - 264
    Cited by:  Papers (15)  |  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (3092 KB)

    The IBM ASTI optimizer provides the foundation for high-order transformations and automatic shared-memory parallelization in the latest IBM XL FORTRAN (XLF) compilers for RS/6000™ and PowerPC® uniprocessors and symmetric multiprocessors (SMPs), and for automatic distributed-memory parallelizationin the IBM XL High-Performance FORTRAN (XLHPF) compiler for the SP2™ distributed-m... View full abstract»

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  • Prefetching and memory system behavior of the SPEC95 benchmark suite

    Publication Year: 1997, Page(s):265 - 286
    Cited by:  Papers (19)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1701 KB)

    This paper presents instruction and data cache miss rates for the SPEC95™ benchmark suite. We have simulated the instruction and data traffic resulting from 500 million instructions of each of the 18 programs. Simulation results show that only a few of the applications place more than modest demands on the memory system. This was noticed for instruction caches, where only a few workloads re... View full abstract»

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  • Simulation/evaluation environment for a VLIW processor architecture

    Publication Year: 1997, Page(s):287 - 302
    Cited by:  Papers (9)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1420 KB)

    We describe the environment used for the simulation and evaluation of a processor architecture based on very long instruction word (VLIW) principles. In this architecture, a program consists of a set of tree instructions, each one containing multiple branches and operations which can be performed simultaneously. The simulation/evaluation environment comprises • An optimizing compiler, which... View full abstract»

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  • Dynamic resource management on distributed systems using reconfigurable applications

    Publication Year: 1997, Page(s):303 - 330
    Cited by:  Papers (7)  |  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (2588 KB)

    Efficient management of distributed resources, under conditions of unpredictable and varying workload, requires enforcement of dynamic resource management policies. Execution of such policies requires a relatively fine-grain control over the resources allocated to jobs in the system. Although this is a difficult task using conventional job management and program execution models, reconfigurable ap... View full abstract»

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  • NStrace: A bus-driven instruction trace tool for PowerPC microprocessors

    Publication Year: 1997, Page(s):331 - 344
    Cited by:  Papers (2)  |  Patents (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1159 KB)

    NStrace is a bus-driven hardware trace facility developed for the PowerPC® family of superscalar RISC microprocessors. It uses a recording of activity on a target processor's bus to infer the sequence of instructions executed during that recording period. NStrace is distinguished from related approaches by its use of an architecture-level simulator to generate the instruction sequence from ... View full abstract»

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  • A programmer's view of performance monitoring in the PowerPC microprocessor

    Publication Year: 1997, Page(s):345 - 356
    Cited by:  Papers (4)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1277 KB)

    Performance monitor (PM) support in on-chip PowerPC® microprocessors is used to analyze processor, software, and system attributes for a variety of workloads. The interface to the PowerPC 604® microprocessor, which we abbreviate “604,” has been externalized to end users. We discuss the enhanced PM support available in an upgrade of the 604, the PowerPC 604e™ micr... View full abstract»

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  • Optimization of TCP segment size for file transfer

    Publication Year: 1997, Page(s):357 - 366
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1128 KB)

    In this paper, we study the problem of optimal Transmission Control Protocol (TCP) segment size for file transfer from hosts to clients. The criterion of optimality is the minimization of the amount of TCP and IP (Internet Protocol) processing by the sender. The parameters that govern the host-processing cost include the cost for processing both the outgoing TCP segments and incoming TCP acknowled... View full abstract»

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  • Recent publications by IBM authors

    Publication Year: 1997, Page(s):367 - 378
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (977 KB)

    The information listed here is supplied by the Institute for Scientific Information and other outside sources. Reprints of the papers may be obtained by writing directly to the first author cited. Journals are listed alphabetically by title; papers are listed sequentially for each journal. View full abstract»

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  • Recent IBM patents

    Publication Year: 1997, Page(s):379 - 392
    IEEE is not the copyright holder of this material | PDF file iconPDF (991 KB)
    Freely Available from IEEE

Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

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Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center