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IBM Journal of Research and Development

Issue 6 • Date Nov. 1998

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Displaying Results 1 - 15 of 15
  • Data compression technology in ASIC cores

    Publication Year: 1998 , Page(s): 725 - 732
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (563 KB)  

    IBM has made its data compression technology available to the industry through the ASIC (application-specific integrated circuit) Blue Logic core program. The papers in this journal describe four of IBM's data compression cores which are in that core library: ALDC (adaptive lossless data compression), JBIG-ABIC (Joint Bi-level Image Group-Adaptive Bi-level Image Compression), MPEG-2 (Moving Picture Experts Group-2), and 401DEC (decompression for the IBM PowerPC 401™ embedded processor). This paper is organized into three main sections: a description of the data types covered by the technology; a presentation of data compression availability through the core library elements; and a brief overview of the papers which follow. View full abstract»

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  • A fast hardware data compression algorithm and some algorithmic extensions

    Publication Year: 1998 , Page(s): 733 - 746
    Cited by:  Papers (12)  |  Patents (36)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1075 KB)  

    This paper reports on work at IBM's Austin and Burlington laboratories concerning fast hardware implementations of general-purpose lossless data compression algorithms, particularly for use in enhancing the data capacity of computer storage devices or systems, and transmission data rates for networking or telecommunications channels. The distinctions between lossy and lossless compression and static and adaptive compression techniques are first reviewed. Then, two main classes of adaptive Lempel-Ziv algorithm, now known as LZ1 and LZ2, are introduced. An outline of early work comparing these two types of algorithm is presented, together with some fundamental distinctions which led to the choice and development of an IBM variant of the LZ1 algorithm, ALDC , and its implementation in hardware. The encoding format for ALDC is presented, together with details of IBM's current fast hardware CMOS compression engine designs, based on use of a content-addressable memory (CAM) array. Overall compression results are compared for ALDC and a number of other algorithms, using the CALGARY data compression benchmark file corpus. More recently, work using small hardware preprocessors to enhance the compression of ALDC on other types of data has shown promising results. Two such algorithmic extensions, BLDC and cLDC , are presented, with the results obtained on important data types for which significant improvement over ALDC alone is achieved. View full abstract»

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  • Design considerations for the ALDC cores

    Publication Year: 1998 , Page(s): 747 - 752
    Cited by:  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (549 KB)  

    The IBM adaptive lossless data compression (ALDC) family of products uses a derivative of Lempel-Ziv encoding to compress data. Several variables affect the compression performance of the ALDC algorithm: data content, history size, and data extent. As ALDC compression is integrated into different applications, restrictions are placed upon these variables that affect the overall compression performance of the system. More complex applications require further support for higher-order data structures such as variable-length segments, error recovery, and expansion. The IBM Blue Logic ALDC and embedded lossless data compression (ELDC) cores have been developed to work in these application environments. These cores and the issues associated with integrating data compression into a system are discussed. View full abstract»

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  • A JBIG-ABIC compression engine for digital document processing

    Publication Year: 1998 , Page(s): 753 - 758
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (498 KB)  

    This paper describes the implementation of a combined JBIG and ABIC compression- decompression engine, which has been integrated into a digital document- processing microcontroller used in imaging applications. View full abstract»

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  • Performance as a function of compression

    Publication Year: 1998 , Page(s): 759 - 766
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (826 KB)  

    This paper discusses the performance of bilevel-image arithmetic coders, ABIC and JBIG, and Lempel-Ziv string compressors, ALDC and BLDC. Images are analyzed for typical and worst-case throughput and latency as a function of compression. A relationship between the compressibility of an image and the throughput performance of the compression algorithm is demonstrated. Generally, throughput performance of the bilevel-image arithmetic coders decreased as image entropy increased. Inversely, the bilevel-image string compressor (BLDC) revealed that increased entropy improved throughput performance. Experimental results based on hardware implementations have been provided and analyzed. View full abstract»

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  • The Qx-coder

    Publication Year: 1998 , Page(s): 767 - 784
    Cited by:  Papers (11)  |  Patents (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1248 KB)  

    The IBM Adaptive Bilevel Image Compression (ABIC) algorithm depends upon the hardware-optimized Q-coder. The Joint Bi-level Image Experts Group (JBIG) settled upon a software-optimized QM-coder. This paper explores the incompatibilities of the hardware- and software-optimized binary arithmetic coding conventions and reports on the solution that allowed a merged Qx-coder in hardware. A unique hardware solution is presented for the termination of the JBIG data stream (CLEARBITS). The probability estimation is presented in a common format. Detailed flowcharts are included in the Appendix. An ASIC core is available that supports both the ABIC and JBIG bilevel data compression standards using this merged Qx-coder. View full abstract»

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  • The IBM JBIG-ABIC Verification Suite

    Publication Year: 1998 , Page(s): 785 - 794
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (717 KB)  

    The IBM JBIG-ABIC Verification Suite is a newly designed verification suite that contains more than 5000 correctly encoded test images. Previously existing verification images in total and consolidated in an ad hoc suite tested only a small fraction of the algorithm and were inadequate. The IBM JBIG-ABIC Verification Suite provides compatibility testing reference data for the ITU-T/ISO JBIG sequential mode and IBM ABIC image compression standards. In this paper, the test images are described and related to the JBIG and ABIC compression standards and options. The verification suite was used to debug and verify the algorithms in the IBM JBIG-ABIC core that is integrated into the Xionics XipChip imaging microcontrollers. View full abstract»

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  • Integrating the MPEG-2 subsystem for digital television

    Publication Year: 1998 , Page(s): 795 - 806
    Cited by:  Patents (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (904 KB)  

    An MPEG-2 subsystem consisting of the transport demultiplexor, audio decoder, and video decoder is described, along with the supporting processor and memory subsystem. This subsystem is directly applicable to set-top box designs used in a digital television broadcast environment. The advantages of an integrated MPEG-2 subsystem consisting of cores from the IBM Blue Logic library are discussed. The integrated architecture supports a shared memory address space implemented using the PowerPC® local bus (PLB) standard high-speed bus. The resulting memory-management improvements for on-screen display (OSD), decoder rate buffers, audio and video clip data, and transport system data are illustrated. The real-time memory bandwidth and latency requirements for processing an MPEG-2 stream also have an impact on the architecture of the subsystem. Additional enhancements are provided for channel changes, time-base changes, error handling, and enhanced processing in the transport by adding more specialized buses. Programming effort is reduced because the software has less responsibility managing data movement through the system and because the same programming method is used to control all of the MPEG-2 functions. View full abstract»

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  • A decompression core for PowerPC

    Publication Year: 1998 , Page(s): 807 - 812
    Cited by:  Papers (21)  |  Patents (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (494 KB)  

    Code size efficiency is a critical parameter in the design of computer systems for embedded applications. This paper describes a method for improving code size efficiency involving the use of compression techniques to reduce the size of the stored code, and on-the-fly hardware decompression at full processor speed for execution. A simple frequency-based encoding scheme for PowerPC® code achieves a typical code size reduction to 60% of the original size. A corresponding decompression core has been implemented for an embedded microprocessor, such as the PowerPC 401™. The compression/decompression scheme operates in a manner transparent to the processor and requires no changes to such tools as compilers, linkers, and loaders. View full abstract»

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  • Modular nets (MNETS): A modular design methodology for computer timers

    Publication Year: 1998 , Page(s): 813 - 830
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1340 KB)  

    This paper describes a modular, graphical, fully implemented CAD tool for building timers to model computer pipelines. The complete system is composed of three parts which can exist independently but have been fully integrated to provide a user-friendly CAD tool. These parts are, first, modular nets (MNETS), a new modeling concept for modular, graphical implementation of pipeline structures of any kind; second, the implementation of various MNETS modules and macros in a VHDL library similar to logic and circuit design libraries; and third, the integration of parts 1 and 2 into an existing graphical entry framework, the EDA Wizard graphical editor. A graphical model is constructed by interconnecting basic building blocks using the graphical tool, similarly to the way circuits and logic are designed. Selection of a menu option will produce a VHDL description of this graphical model, which can subsequently be simulated on a VHDL simulator. This paper concentrates on part 1, the features of MNETS which make it inherently modular and consequently graphical. The two crucial requirements, namely the construct for storing of state and a control mechanism for the passing of state, are unique to MNETS and are discussed in detail, with comparisons to other methodologies. A brief discussion of some features and macros available in the existing MNETS library is included, as well as one simple modeling example. This library can be accessed on the IBM Andrew file system, AFS. A detailed MNETS user/design manual is available which describes MNETS in detail, as well as the library, memory hierarchy design, and modeling. View full abstract»

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  • Recent publications by IBM authors

    Publication Year: 1998 , Page(s): 831 - 838
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (645 KB)  

    The information listed here is supplied by the Institute for Scientific Information and other outside sources. Reprints of the papers may be obtained by writing directly to the first author of cited. Journals are listed alphabetically by title; papers are listed sequentially for each journal. View full abstract»

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  • Recent IBM patents

    Publication Year: 1998 , Page(s): 839 - 860
    Save to Project icon | PDF file iconPDF (1353 KB)  
    Freely Available from IEEE
  • Author index for papers in Volume 42

    Publication Year: 1998 , Page(s): 861 - 866
    Save to Project icon | PDF file iconPDF (275 KB)  
    Freely Available from IEEE
  • Subject index for papers in Volume 42

    Publication Year: 1998 , Page(s): 867 - 873
    Save to Project icon | PDF file iconPDF (424 KB)  
    Freely Available from IEEE
  • Errata [Addenda]

    Publication Year: 1998 , Page(s): 874
    Save to Project icon | PDF file iconPDF (48 KB)  
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Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center