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IBM Journal of Research and Development

Issue 3 • Date May 1999

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Displaying Results 1 - 14 of 14
  • Preface

    Page(s): 243 - 244
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1361 KB)  

    Progress in MOS integrated-circuit technology has been largely dominated by the scaling of device feature sizes. For the production of advanced CMOS logic devices with minimum feature sizes in the sub-0.1-µm regime, one of the areas of device fabrication that will limit future CMOS scaling is the continued reduction in the gate dielectric film thickness. This issue of the IBM Journal of Research and Development focuses on the processes and materials that are required to produce reliable CMOS devices with ultrathin gate dielectric films. View full abstract»

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  • Scaling the gate dielectric: Materials, integration, and reliability

    Page(s): 245 - 264
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1322 KB)  

    In this paper a review of the more “fundamental” concerns regarding the scaling of the gate dielectric in the ultrathin regime is presented. Material issues are discussed pertaining to the integration of silicon oxynitride and oxide/nitride stacked layers and how such films might reduce or minimize boron penetration problems and address leakage current and reliability concerns. A methodology is presented to calculate device and chip lifetimes for MOS structures on the basis of data extracted from voltage- and temperature-accelerated measurements. Some integration issues regarding higher-k materials are also discussed because of their ability to solve the scaling problem. However, difficulties are involved in integrating them into a CMOS process flow. View full abstract»

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  • Growth and characterization of ultrathin nitrided silicon oxide films

    Page(s): 265 - 286
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1157 KB)  

    This paper reviews recent progress in understanding microstructural and growth-mechanistic aspects of ultrathin (<4 nm) oxynitride films for gate dielectric applications. Different techniques for characterizing these films are summarized. We discuss several nitridation methods, including thermal (oxy)nitridation in NO, N2O, and N2 as well as a variety of deposition methods. We show that a basic understanding of the gas-phase and thin-film oxygen and nitrogen incorporation chemistries facilitates the processing of layered oxynitride nanostructures with desirable electrical properties. View full abstract»

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  • Nitrous oxide (N2O) processing for silicon oxynitride gate dielectrics

    Page(s): 287 - 300
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (768 KB)  

    The gas-phase chemistry of silicon oxynitridation in N2O has been investigated. From an evaluation of available kinetic data, we have developed a model for the thermal decomposition of gaseous N2O. To quantify heat transfer between the N2O gas and the wall of the furnace, we introduce the concept of referencing to an N2 gas-temperature profile, measured in an oxidation furnace. Using this model, we can account for the increase with flow rate and temperature of the NO concentration in the N2O decomposition product, and the self-heating during decomposition, for furnace processing. This change in gaseous NO concentration translates to a higher nitrogen content and lower growth rate for the silicon oxynitride. For rapid thermal and other short-gas-residence-time systems, we show that atomic oxygen is present at the Si wafer, and that this removes previously incorporated nitrogen. View full abstract»

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  • Ultrathin nitrided gate dielectrics: Plasma processing, chemical characterization, performance, and reliability

    Page(s): 301 - 326
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1837 KB)  

    The incorporation of nitrogen (N) atoms into ultrathin gate dielectrics 1) at monolayer levels at Si-SiO2 interfaces reduces tunneling current and defect generation; 2) in bulk nitrides, as in oxide-nitride-oxide (ONO) or oxide-nitride (ON) composite structures, allows the use of physically thicker films without reduced capacitance compared to single-layer oxides; and 3) in nitrided layers at the polycrystalline Si-dielectric interface or in ON dielectrics reduces boron (B) atom out-diffusion from heavily doped p+ polycrystalline silicon gate electrodes into oxide gate dielectrics. The results presented in this review demonstrate that N atoms can be selectively and independently incorporated into different parts of the gate dielectric by low-temperatureremote-plasma-assisted processing. When combined with low-thermal-budget rapid thermal annealing, this yields ultrathin gate dielectrics with performance and reliability which generally exceeds that of single-layer thermally grown oxides. The devices addressed in this paper include n-MOS and p-mos field-effect transistors (FETs) with oxide-equivalent thicknesses of less than 2 nm. View full abstract»

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  • Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides

    Page(s): 327 - 337
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (907 KB)  

    The electrical characteristics (C-V and I-V) of n+- and p+-polysilicon-gated ultrathin-oxide capacitors and FETs were studied extensively to determine oxide thickness and to evaluate tunneling current. A quantum-mechanical model was developed to help understand finite inversion layer width, threshold voltage shift, and polysilicon gate depletion effects. It allows a consistent determination of the physical oxide thickness based on an excellent agreement between the measured and modeled C-V curves. With a chip standby power of ≤0.1 W per chip, direct tunneling current can be tolerated down to an oxide thickness of 15–20 Å. However, transconductance reduction due to polysilicon depletion and finite inversion layer width effects becomes more severe for thinner oxides. The quantum-mechanical model predicts higher threshold voltage than the classical model, and the difference increases with the electric field strength at the silicon/oxide interface. View full abstract»

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  • Cost-effective cleaning and high-quality thin gate oxides

    Page(s): 339 - 350
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (663 KB)  

    Some recent findings in the area of wafer cleaning and thin oxide properties are presented in this paper. Results are shown for a practical implementation of a simplified cleaning concept that combines excellent performance in terms of metal and particle removal with low chemical and DI-water consumption. The effect of organic contamination on ultrathin gate-oxide integrity is illustrated, and the feasibility of using ozonated DI water as an organic removal step is discussed. Metal outplating from HF and HF/HCl solutions is investigated. Also, the final rinsing step is critically evaluated. It is demonstrated that Si surface roughness without the presence of metal contaminants does not degrade gate-oxide integrity. Finally, some critical remarks on the reliability measurements for ultrathin gate oxides are given; it is shown that erroneous conclusions can be drawn from constant-current charge-to-breakdown measurements. View full abstract»

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  • Characterization of silicon surface preparation processes for advanced gate dielectrics

    Page(s): 351 - 326
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (877 KB)  

    This paper gives a short overview of issues associated with the surface preparation of silicon surfaces for advanced gate dielectrics and the appearance and nature of the wafer surface after different chemical treatments. The main portion of the paper demonstrates the use of electrochemical open-circuit potential (OCP) measurements as a simple and powerful technique to investigate and characterize wet silicon surface-preparation processes. This technique provides unique information about the evolution of semiconductor surface reactions in wet- chemical environments and permits the investigation of the kinetics of oxidation and etching processes in situ and in real time. Very good agreement between results obtained by this technique and results from multiple internal reflection-Fourier transform infrared spectroscopy (MIR-FTIR), X-ray photoelectron spectroscopy (XPS), spectroscopic ellipsometry (SE), and contact-angle studies is presented in this paper. A model is also presented which permits the correlation of the measured open circuit potential difference to the thickness of a growing native oxide. The etching behavior of an ultrathin thermally grown silicon oxide layer in hydrofluoric acid (HF) is discussed as a new result obtained using the OCP technique. View full abstract»

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  • (Ba,Sr)TiO3 dielectrics for future stacked- capacitor DRAM

    Page(s): 367 - 382
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1770 KB)  

    Thin films of barium-strontium titanate (Ba,Sr)TiO3 (BSTO) have been investigated for use as a capacitor dielectric for future generations of dynamic random-access memory (DRAM). This paper describes progress made in the preparation of BSTO films by liquid-source metal-organic chemical vapor deposition (LS-MOCVD) and the issues related to integrating films of BSTO into a DRAM capacitor. Films of BSTO deposited on planar Pt electrodes meet the electrical requirements needed for future DRAM. The specific capacitance and charge loss are found to be strongly dependent on the details of the BSTO deposition, the choice of the lower electrode structure, the microstructure of the BSTO, the post-electrode thermal treatments, BSTO dopants, and thin-film stress. Films of BSTO deposited on patterned Pt electrodes with a feature size of 0.2 µm are found to have degraded properties compared to films on large planar structures, but functional bits have been achieved on a DRAM test site at 0.20-µm ground rules. Mechanisms influencing specific capacitance and charge loss of BSTO films are described, as are therequirements for the electrode and barrier materials used in stacked-capacitor structures, with emphasis given to the properties of the Pt/TaSi(N) electrode/barrier system. Major problems requiring additional investigation are outlined. View full abstract»

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  • Titanium dioxide (TiO2)-based gate insulators

    Page(s): 383 - 392
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1254 KB)  

    Titanium dioxide has been deposited on silicon for use as a high-permittivity gate insulator in an effort to produce low-leakage films with oxide equivalent thicknesses below 2.0 nm. Excellent electrical characteristics can be achieved, but TEM and electrical measurements have shown the presence of a low-resistivity interfacial layer that we take to be SiO2. The leakage current follows several mechanisms depending on the bias voltage. Reasonably good agreement has been seen between current-voltage measurements and a 1D quantum transport model. View full abstract»

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  • Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations

    Page(s): 393 - 406
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1056 KB)  

    Device characteristics and reliability in a 3.3-V logic CMOS technology with various gate oxidation and nitridation processes are described. The technology was designed to extend 3.3-V devices to the ultimate dielectric reliability limit while maintaining strict manufacturing cost control. A nitrided gate oxide provided the means to maintain hot-electron reliability at the level of the previous iteration, but at higher performance and lower processing cost. Conventional furnace processes in nitrous and nitric oxide, high-pressure oxidation in oxygen and nitrous oxide, and rapid-thermal processes using nitrous and nitric oxide were investigated. We found that the concomitant variations in fixed charge and thermal budget have a significant influence on both n-FET and p-FET device parameters such as threshold voltage, carrier mobility, and inverse short-channel effect (ISCE). Reliability effects, such as charge to breakdown (QBD), hot-electron degradation,and negative-bias temperature instability (NBTI) were examined and correlated with the nitrogen profile in the gate dielectric. Secondary ion mass spectroscopy (SIMS) profiles were used to characterize the oxidation techniques and to correlate gate dielectric composition to the parametric and reliability parameters. View full abstract»

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  • Key measurements of ultrathin gate dielectric reliability and in-line monitoring

    Page(s): 407 - 416
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (445 KB)  

    High-performance CMOS products depend upon the reliability of ultrathin gate dielectrics. In this paper a methodology for measuring thin gate dielectric reliability is discussed in which the focus is upon the elements of those test structures used in the evaluation, the design of the reliability stress matrix, and the generation of engineering design models. Experimental results are presented which demonstrate the reliability of ultrathin gate dielectrics measured on a wide variety of test structures with dielectric thicknesses ranging from 7 to 3.5 nm. An overview is provided for thin gate oxide reliability that was measured on integrated functional chips—high-performance microprocessors and static random-access memory (SRAM) chips. The data from these measurements spanned the period from early process and device development to full production. Manufacturing in-line monitoring for thin gate dielectric yield and reliability is also discussed, with several case histories presented which show the effectiveness of monitors in detecting process-induced dielectric failures. Finally, causes of oxide fails are discussed, leading to the process actions necessary for controlling thin gate dielectric defects. View full abstract»

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  • Recent publications by IBM authors

    Page(s): 417 - 430
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (3350 KB)  

    The information listed here is supplied by the Institute for Scientific Information and other outside sources. Reprints of the papers may be obtained by writing directly to the first author cited. Journals are listed alphabetically by title; papers are listed sequentially for each journal. View full abstract»

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  • Recent IBM patents

    Page(s): 443 - 448
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    Freely Available from IEEE

Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

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Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center