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IBM Journal of Research and Development

Issue 2.3 • Date March 2002

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Displaying Results 1 - 17 of 17
  • Preface

    Publication Year: 2002, Page(s):119 - 120
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (29 KB)

    This issue, “Scaling CMOS to the Limit,” comes at a point in the evolution of CMOS where, on the one hand, the technology has achieved the status of a prime mover of society, the “silicon age,” in which past visions of a dollar per MIPS (million instructions per second) of computer power and a dollar per megabyte of memory have come to pass; while on the other hand the ... View full abstract»

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  • SOI technology for the GHz era

    Publication Year: 2002, Page(s):121 - 131
    Cited by:  Papers (68)  |  Patents (40)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (582 KB)

    Silicon-on-insulator (SOI) CMOS offers a 20–35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-µm generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI ... View full abstract»

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  • Beyond the conventional transistor

    Publication Year: 2002, Page(s):133 - 168
    Cited by:  Papers (130)  |  Patents (67)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (2124 KB)

    This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-sil... View full abstract»

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  • Maintaining the benefits of CMOS scaling when scaling bogs down

    Publication Year: 2002, Page(s):169 - 180
    Cited by:  Papers (69)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (497 KB)

    A survey of industry trends from the last two decades of scaling for CMOS logic is examined in an attempt to extrapolate practical directions for CMOS technology as lithography progresses toward the point at which CMOS is limited by the size of the silicon atom itself. Some possible directions for various specialized applications in CMOS logic are explored, and it is further conjectured that doubl... View full abstract»

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  • Why BiCMOS and SOI BiCMOS?

    Publication Year: 2002, Page(s):181 - 186
    Cited by:  Papers (8)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (179 KB)

    Silicon technology development is at a crossroads, following an exponential rate of progress for more than thirty years. While CMOS (complementary metal—oxide-semiconductor) will remain the backbone of digital logic, silicon technology will evolve in directions driven by system needs that are not met by CMOS alone. It is argued that BiCMOS (bipolar complementary metal—oxide-semicondu... View full abstract»

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  • Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

    Publication Year: 2002, Page(s):187 - 212
    Cited by:  Papers (42)  |  Patents (54)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (981 KB)

    Significant challenges face DRAM scaling toward and beyond the 0.10-µm generation. Scaling techniques used in earlier generations for the array-access transistor and the storage capacitor are encountering limitations which necessitate major innovation in electrical operating mode, structure, and processing. Although a variety of options exist for advancing the technology, such as low-voltag... View full abstract»

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  • CMOS design near the limit of scaling

    Publication Year: 2002, Page(s):213 - 222
    Cited by:  Papers (84)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (410 KB)

    Beginning with a brief review of CMOS scaling trends from 1 µm to 0.1 µm, this paper examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length. Both the standby power and the act... View full abstract»

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  • Effect of increasing chip density on the evolution of computer architectures

    Publication Year: 2002, Page(s):223 - 234
    Cited by:  Papers (4)  |  Patents (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (163 KB)

    Trends in lithography and process technology indicate that billion-transistor computer chips will be possible well before the end of the decade. Such a large number of transistors could be used to implement dynamic learning techniques to improve the performance of a processor for many applications. However, the efficiency of use of transistors in this manner is not high. A more attractive use of t... View full abstract»

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  • Power-constrained CMOS scaling limits

    Publication Year: 2002, Page(s):235 - 244
    Cited by:  Papers (45)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (368 KB)

    The scaling of CMOS technology has progressed rapidly for three decades, but may soon come to an end because of power-dissipation constraints. The primary problem is static power dissipation, which is caused by leakage currents arising from quantum tunneling and thermal excitations. The details of these effects, along with other scaling issues, are discussed in the context of their dependence on a... View full abstract»

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  • Interconnect opportunities for gigascale integration

    Publication Year: 2002, Page(s):245 - 263
    Cited by:  Papers (49)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (719 KB)

    Throughout the past four decades, semiconductor technology has advanced at exponential rates in both productivity and performance. In recent years, multilevel interconnect networks have become the primary limit on the productivity, performance, energy dissipation, and signal integrity of gigascale integration. Consequently, a broad spectrum of novel solutions to the multifaceted interconnect probl... View full abstract»

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  • Reliability limits for the gate insulator in CMOS technology

    Publication Year: 2002, Page(s):265 - 286
    Cited by:  Papers (57)  |  Patents (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (274 KB)

    Aggressive scaling of the thickness of the gate insulator in CMOS transistors has caused the quality and reliability of ultrathin dielectrics to assume greater importance. This paper reviews the physics and statistics of dielectric wearout and breakdown in ultrathin SiO2-based gate dielectrics. Estimating reliability requires an extrapolation from the measeurment conditions (e.g., highe... View full abstract»

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  • CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics

    Publication Year: 2002, Page(s):287 - 298
    Cited by:  Papers (36)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (263 KB)

    The limitations of reliability of silicon dioxide dielectric for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is interpreted. Experimental data over a wide range of oxide thickness (TOX), voltage, and temperature were gathered using structure... View full abstract»

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  • Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?

    Publication Year: 2002, Page(s):299 - 315
    Cited by:  Papers (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (309 KB)

    The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed. For gate stacks, considerable progress has been made in optimizing oxide/nitride and oxynitride dielectrics to reduce boron penetration and dielectric leakage compared to pure SiO2 in order to allow sub-2-nm dielectrics. Several promising alternative material candidates exist for 1-nm equ... View full abstract»

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  • Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation

    Publication Year: 2002, Page(s):317 - 338
    Cited by:  Papers (6)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (804 KB)

    Since the advent of the Si-based integrated circuit, ever-increasing function has been available at reduced cost and with reduced consumption of power. This “semiconductor revolution” has been possible because semiconductor devices have the unique feature that as they become smaller they also become faster, consume less power, become cheaper per circuit, and enable more function per ... View full abstract»

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  • Process modeling for future technologies

    Publication Year: 2002, Page(s):339 - 346
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (133 KB)

    Process modeling is an integral portion of technology computer-aided design (TCAD) and can be used to predict device structures and doping. Truly predictive process modeling has proven to be an elusive goal, because the controlling physics is complicated and difficult to investigate experimentally. The current state of process modeling is reviewed, and current and future challenges are discussed. ... View full abstract»

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  • New insights into carrier transport in n-MOSFETs

    Publication Year: 2002, Page(s):347 - 357
    Cited by:  Papers (18)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (228 KB)

    This paper discusses recent experimental investigations of the relation between low-field effective mobility and effective injection velocity of electrons from the source into the channel, as manifested in current drive, of deeply scaled n-MOSFETs. It is first established that the effective velocity in electrostatically sound, “well-tempered” scaled devices, for example with drain-in... View full abstract»

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  • Preparation of manuscripts for the IBM Journal of Research and Development

    Publication Year: 2002, Page(s):359 - 360
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (34 KB)

    The manuscript must be a report of significant new work, a new review or overview, or a combination of the above-and be targeted toward the general technical reader. Although a shorter version may have been published (or submitted for publication) elsewhere—for example, in a rapid publication such as Applied Physics Letters or in a conference proceedings-the manuscript may be acceptable if ... View full abstract»

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Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

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Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center