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IBM Journal of Research and Development

Issue 6 • Date Nov. 2002

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Displaying Results 1 - 13 of 13
  • Preface

    Page(s): 647
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (20 KB)  

    The past decade has witnessed the advent of system-on-a-chip (SoC) ASIC designs. SoC ASICs require a combination of high-speed performance, state-of-the-art packaging technology, and the integration of complex capabilities onto a single chip, all supported by design and development tools. View full abstract»

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  • The IBM ASIC/SoC methodology—A recipe for first-time success

    Page(s): 649 - 660
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    This paper describes the methodology employed by the IBM Microelectronics Division for the design of its Blue Logic® application-specific integrated circuits (ASICs) and system-on-a-chip (SoC) designs. This methodology is used by both IBM ASIC and SoC designers, as well as OEM customers. A key focus of the IBM ASIC/SoC methodology, outlined in the first section of this paper, is the first-time-right methods of design and verification that maximize correct operation of the chip upon product integration. The second section of this paper describes advances in methodology that deal with the physical effects of shrinking device geometries and enable design using the performance and density capabilities available in the new technologies, and methodology advances that have improved design turnaround time (TAT) for large, complex designs. Upcoming nanometer-level technologies present new opportunities to integrate systems on a single chip, including functional components of mixed libraries and mixed analog and digital design. The final section of this paper outlines strategies that are enabling SoC design at these levels. View full abstract»

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  • Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering

    Page(s): 675 - 689
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (609 KB)  

    This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM third-generation embedded dynamic random-access memory (DRAM) for the IBM Blue Logic® 0.11-µm application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamental DRAM core function, user interface, test, and diagnosis. Macro operation and organization are detailed and contrasted with traditional DRAM designs. The use of BIST, a key enabler for embedded DRAM, is discussed while highlighting innovations required by the embedded DRAM. View full abstract»

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  • Early analysis tools for system-on-a-chip design

    Page(s): 691 - 707
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (173 KB)  

    The paper describes the need for early analysis tools to enable developers of today's system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic® Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs and outline how this performance analysis capability can be integrated into an overall environment for efficient SoC design. View full abstract»

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  • Preface: Packaging

    Page(s): 709
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (27 KB)  

    In 1993, IBM began replacing bipolar emitter-coupled logic (ECL) in its large mainframe computers with complementary metal-oxide semiconductor (CMOS) logic because of the very high integration density of CMOS, its high switching speed, lower switching current, and excellent reliability. Advances in CMOS microprocessor technology have had a spillover effect on packaging technology. The increased functionality and density of CMOS-based control chips, along with the use of surface-mount technology, have resulted in the denser packaging required to support multichip modules (MCMs). View full abstract»

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  • A power, packaging, and cooling overview of the IBM eServer z900

    Page(s): 711 - 738
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    This paper provides an overview of the power, packaging, and cooling aspects of the IBM eServer z900 design. The semiconductor processor chips must be supported and protected in a mechanical structure that has to provide electrical interconnects while maintaining the chip junction temperature within specified limits. The mechanical structure should be able to withstand shock and vibrations during transportation or events such as earthquakes. The processor chips require electrical power at well-regulated voltages, unaffected by the ac-line voltage and load current fluctuations. The acoustical and electromagnetic noise produced by the hardware must be within the limits set by national regulatory agencies, and the electronic operations must be adequately protected from disruption caused by electromagnetic radiation. For high availability, the power, packaging, and cooling hardware must have redundancy and the ability to be maintained while the system is operating. This paper first overviews the packaging hardware, followed by a description of the first- and second-level packaging, which includes the mother board and the multichip module. Thermal management is discussed from the point of view of both the multichip module and the overall system. Power conversion, management, and distribution are presented next. Finally, the design aspects involved with meeting the requirements of electromagnetic compatibility, acoustics, and immunity to shock, vibration, and earthquakes are discussed. View full abstract»

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  • High-end server low-temperature cooling

    Page(s): 739 - 751
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (438 KB)  

    The IBM S/390® G4 CMOS system, first shipped in 1997, was the first high-end system to use refrigeration. The decision to employ refrigeration cooling instead of other cooling options such as high-flow air cooling or various water-cooling schemes focused on the potential system performance improvement obtainable by lowering coolant temperatures using a refrigeration system. This paper reviews the historical background of refrigeration from its use in the early 1800s to its implementation in computer systems in the early 1990s. The advantages and disadvantages of using refrigeration in the cooling of computer systems are examined. The advantages have outweighed the disadvantages, leading to the first use by IBM of refrigeration in cooling the S/390 G4 server. The design of the refrigeration system for the S/390 G4 system is described in detail, and some of the key parametric studies that contributed to the final design are described. View full abstract»

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  • Design and analysis of a scheme to mitigate condensation on an assembly used to cool a processor module

    Page(s): 753 - 761
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (591 KB)  

    System performance of an IBM RS/6000® workstation was improved by cooling to sub-ambient temperatures the CMOS circuits of a single-chip module (SCM) mounted on a card. However, when refrigeration temperatures are sufficiently low, the temperature of all or a portion of the card on which the module is mounted can fall below the environmental dew point, resulting in unwanted condensation. Strategically placed heaters can maintain the temperature of the card surface above the dew point, but at the expense of increasing the total heat load the refrigeration unit must remove from the system. A 3D finite element analysis was used to investigate some of the key parameters that affect the thermal packaging design of a refrigeration-cooled low-temperature processor module with the objective of preventing condensation on exposed module card surfaces with minimal power input to the added heaters. View full abstract»

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  • Land grid array sockets for server applications

    Page(s): 763 - 778
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1097 KB)  

    The design and performance of land grid array (LGA) sockets are discussed with respect to high-performance server applications. Motivations for the use of this technology are presented, and the specific challenges associated with its application are discussed from a mechanical perspective. A variety of mechanical performance considerations are identified for LGA socket technologies, and a detailed evaluation of competing socket-actuation designs is presented using finite element structural analysis. Some design approaches are shown to suffer from excessive mechanical flexure, which can consume the allowable range of motion of the contact, resulting in excessive contact load variation within the LGA. Statistical considerations for the mechanical deflections and tolerances that contribute to range-of-motion consumption are developed using Monte Carlo techniques, and a parametric study of the mechanical design variables that influence contact load variation within the LGA is presented. View full abstract»

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  • An advanced multichip module (MCM) for high-performance UNIX servers

    Page(s): 779 - 804
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (3176 KB)  

    In 2001, IBM delivered to the marketplace a high-performance UNIX®-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-µm pads on 200-µm centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm × 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology. View full abstract»

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  • Issues and strategies for the physical design of system-on-a-chip ASICs

    Page(s): 661 - 674
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (245 KB)  

    The density and performance of advanced silicon technologies have made system-on-a-chip ASICs possible. SoCs bring together a diverse set of functions and technology features on a single die of enormous complexity. The physical design of these complex ASICs requires a rich set of functional elements that integrate efficiently with a set of design flows and tools productive enough to meet product requirements successfully, without consuming more time or design resources than a simpler design. The architecture described, including functional libraries and physical design conventions, enables the creation of multiple SoC ASIC designs from a common infrastructure that addresses silicon integration, electrical robustness, and packaging challenges. An implementation strategy follows from this design infrastructure that includes hierarchical design concepts, placement, routing, and verification processes. View full abstract»

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  • Author index for papers Volume 46

    Page(s): 805 - 810
    Save to Project icon | PDF file iconPDF (52 KB)  
    Freely Available from IEEE
  • Subject index for papers in Volume 46

    Page(s): 811 - 816
    Save to Project icon | PDF file iconPDF (48 KB)  
    Freely Available from IEEE

Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center