By Topic

IBM Journal of Research and Development

Issue 4.5 • Date July 2005

Filter Results

Displaying Results 1 - 21 of 21
  • Preface

    Publication Year: 2005 , Page(s): 503 - 504
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (36 KB)  

    The heart and soul of all computer systems remains the microprocessor. In this issue we describe two new microprocessors, the POWER5™ and Cell microprocessors. Each is innovative in its approach and is part of a total system design. Each leverages technology and uses the available increased transistor density to incorporate more system function onto a single die than prior systems have done. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • POWER5 system microarchitecture

    Publication Year: 2005 , Page(s): 505 - 521
    Cited by:  Papers (79)  |  Patents (21)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    This paper describes the implementation of the IBM POWER5™ chip, a two-way simultaneous multithreaded dual-core chip and systems based on it. With a key goal of maintaining both binary and structural compatibility with POWER4™ systems, the POWER5 microprocessor allows system scalability to 64 physical processors. A POWER5 system allows both single-threaded and multithreaded execution modes. In single-threaded execution mode, a POWER5 system allows for higher performance than its predecessor POWER4 system at equivalent frequencies. In multithreaded execution mode, the POWER5 microprocessor implements dynamic resource balancing to ensure that each thread receives its fair share of system resources. Additionally, software-settable thread priority is enforced by the POWER5 hardware. To conserve power, the POWER5 chip implements dynamic power management that allows reduced power consumption without affecting performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Advanced virtualization capabilities of POWER5 systems

    Publication Year: 2005 , Page(s): 523 - 532
    Cited by:  Papers (7)  |  Patents (7)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (213 KB)  

    IBM POWER5™ systems combine enhancements in the IBM PowerPC™ processor architecture with greatly enhanced firmware to significantly increase the virtualization capabilities of IBM POWER™ servers. The POWER hypervisor, the basis of the IBM Virtualization Engine™ technologies on POWER5 systems, delivers leading-edge mainframe virtualization technologies to the UNIX® marketplace. In addition to being able to create computing-intensive partitions with dedicated resources (processors, memory, and I/O adapters), customers can harness idle processor capacity to configure micropartitions with virtualized resources in order to consolidate many AIX™, i5/OS™, and Linux® servers onto a single platform. The POWER hypervisor provides support for virtualized processors, an IEEE virtual local area network (VLAN)-compatible virtual Ethernet switch, virtual small computer system interface (VSCSI) adapters, and virtual consoles. Many of these features are dependent upon, or take advantage of, the new facilities provided in the POWER5 processor, including the hypervisor decrementer, a fast page mover, and simultaneous multithreading support. The technology behind the virtualization capabilities that are available on the POWER5 servers, enabling customers to better utilize the industry-leading computing capacity of the POWER5 processor, is discussed in this paper. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Operating system exploitation of the POWER5 system

    Publication Year: 2005 , Page(s): 533 - 539
    Cited by:  Papers (6)  |  Patents (12)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (105 KB)  

    The POWER5™ system incorporates several features designed to improve performance by eliminating bottlenecks and accelerating common functions used in operating systems. This paper discusses how two of the supported operating systems for POWER5—AIX® and Linux™—make use of these features to deliver improved system scalability and performance. In particular, the overheads for synchronizing translation-lookaside buffer (TLB) invalidations between processors, and for ensuring that the instruction cache is kept coherent by software, have been removed. The POWER5 simultaneous multithreading (SMT) implementation has features which allow operating systems to optimize the system for the kinds of applications being executed. We discuss how the operating systems approach the problems of scheduling tasks across the system, of determining when to switch processors between single-threaded (ST) and SMT mode, and of accounting accurately for CPU usage when in the SMT mode. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems

    Publication Year: 2005 , Page(s): 541 - 553
    Cited by:  Papers (11)  |  Patents (7)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    This paper describes the methods and simulation techniques used to verify the functional correctness and performance attributes of the IBM POWER5™ microprocessor and the eServer™ p5 systems based on it. The approaches used were based on migrating the best practices that had been used to verify the POWER4™ chip. The POWER5 chip design posed new challenges to the simulation team with the addition of simultaneous multithreading (SMT) and dynamic power management (DPM). In addition, there was further integration of cache and memory subsystem function onto the POWER5 chip. Since the design complexity had increased from the POWER4 design, the use of test plan coverage tools and techniques was expanded to ensure the maximum effectiveness of each simulation cycle run. A new toolset was also employed to improve the utilization of the large pool of computers used to run batch simulation jobs and to provide more efficient fail reproduction and bug fix management. For the system-level verification, a new test-case-generation tool was utilized which allowed for more targeted testing through a deeper knowledge of the system topology. In parallel with the mainline functional validation, verification of reliability functions and performance attributes also had increased focus for the POWER5 design. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Characterization of simultaneous multithreading (SMT) efficiency in POWER5

    Publication Year: 2005 , Page(s): 555 - 564
    Cited by:  Papers (7)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    Coarse-grained multithreading, the switching of threads to avoid idle processor time during long-latency events, has been available on IBM systems since 1998. Simultaneous multithreading (SMT), first available on the POWER5™ processor, moves beyond simple thread switching to the maintenance of two thread streams that are issued as continuously as possible to ensure the maximum use of processor resources. Because SMT has the potential of increasing processor efficiency and correspondingly increasing the amount of work done for a given time span, the reader might suppose that SMT would exhibit a performance gain for all workloads. This is true for most workloads, but is not true in some exceptional cases. In SMT mode, the processor resources—register sets, caches, queues, translation buffers, and the system memory nest—must be shared by both threads, and conditions can occur that degrade or even obviate SMT performance improvement. The POWER4™ and POWER5 processors have very powerful performance monitor (PM) toolsets that can help the user to determine what is occurring in workloads that may not be providing expected SMT gains. In this paper, the results of measured differences among workloads having large, medium, small, and even negative SMT performance gains are presented along with an approach to investigating workloads to determine the source of SMT performance gain limits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Functional formal verification on designs of pSeries microprocessors and communication subsystems

    Publication Year: 2005 , Page(s): 565 - 580
    Cited by:  Papers (3)  |  Patents (6)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (263 KB)  

    This paper discusses our experiences and results in applying functional formal verification (FFV) techniques to the design of the IBM pSeries® microprocessor and communication subsystem. We describe the evolution of FFV deployment across several generations of this product line, including tool and algorithmic improvements, as well as methodological improvements for prioritizing the portions of the design that should be considered for formal verification coverage. Improvements made in the formal verification toolset, including the introduction of semiformal verification and bounded-model-checking algorithms, have allowed increasingly larger partitions to become candidates for formal coverage. Other tool enhancements, such as phase-abstraction techniques to deal with clock gating schemes, are presented. Overall, numerous complex design defects were discovered using formal techniques across the microprocessor and communication subsystem, many of which would likely have escaped to the test floor. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Using microcode in the functional verification of an I/O chip

    Publication Year: 2005 , Page(s): 581 - 588
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    The IBM pSeries® clustered and parallel processing systems require high-speed, low-latency communication among processor nodes. The 2-Link Switch Network Interface and 4-Link Switch Network Interface for the pSeries High Performance Switch are the adapters which provide the communication infrastructure for the pSeries p655 and p690 servers. A unique approach was used during the functional verification of these adapters that yielded benefits over the methodology used for the previous-generation product—the SP™ Switch2 Adapter. The approach used on the Switch Network Interface introduced the concept of using microcode during the functional verification process. This paper gives an overview of functional verification, followed by a description of the SP Switch2 Adapter and the Switch Network Interface. The verification methodologies used on these adapters are described and compared. Finally, the benefits of implementing hardware/software co-verification on the Switch Network Interface throughout the development cycle are described. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Introduction to the Cell multiprocessor

    Publication Year: 2005 , Page(s): 589 - 604
    Cited by:  Papers (209)  |  Patents (34)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (342 KB)  

    This paper provides an introductory overview of the Cell multiprocessor. Cell represents a revolutionary extension of conventional microprocessor architecture and organization. The paper discusses the history of the project, the program objectives and challenges, the design concept, the architecture and programming models, and the implementation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Preface

    Publication Year: 2005 , Page(s): 605 - 606
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (40 KB)  

    Electronic packaging has been defined as the “branch of science and technology relating to the establishment of electrical interconnections and appropriate housing for electrical circuitry.”1 It serves the following four major functions for microelectronics: interconnection of electrical signals, mechanical and environmental protection of circuits, distribution of electrical energy (i.e., power), and dissipation of heat energy generated by semiconductor devices. These four functions continue to generate advances in microelectronic packaging technology. Looking to the future, as further improvements in semiconductor performance become more challenging and expensive, optimization at multiple levels in packaging will be required in order to maintain increases in system-level performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Microstructure and mechanical properties of lead-free solders and solder joints used in microelectronic applications

    Publication Year: 2005 , Page(s): 607 - 620
    Cited by:  Papers (26)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (749 KB)  

    The replacement of lead (Pb)-bearing solders used in the electronic industry with Pb-free solders will become a reality in the near future. Several promising Pb-free solders have recently been identified, including Sn-0.7Cu, Sn-3.5Ag, Sn-3.8Ag-0.7Cu, and Sn-3.5Ag-4.8Bi (in wt.% with slight variations in composition). These are all Sn-rich solders with melting temperatures between 210°C and 227°C, and are recommended for various soldering applications, including surface mount technology (SMT), plated-through-hole (PTH), ball grid array (BGA), flip-chip bumping, and others. Although a considerable amount of information on Pb-free solders has been published in the last few years, the database on these new materials is still at an infant stage compared with that for Pb-containing solders. This paper addresses several aspects of the current fundamental materials understanding associated with Pb-free solders and various issues regarding their imminent use in electronic interconnect applications, including microstructure-processing-property relations, mechanical properties, interfacial reactions, and the thermal-fatigue life and failure mechanisms of Pb-free solder joints. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-cost wafer bumping

    Publication Year: 2005 , Page(s): 621 - 639
    Cited by:  Papers (27)  |  Patents (29)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    As the demand for flip-chip interconnects mounts across an increasingly large spectrum of products and technologies, several wafer-bumping processes have been developed to produce the small solder features required for this interconnect technology. These processes differ significantly in complexity and commensurate cost. Recently, a new bumping process developed at IBM Research called injection-molded solder, or IMS, has shown the capability to combine low-cost attributes with high-end capabilities. The development of IMS technology was driven by the need to reduce wafer-bumping costs while simultaneously addressing the conflicting needs of increasing wafer dimensions to 300 mm, decreasing bump and pitch dimensions below 75 µm on 150-µm centers, and optimal Pb-free alloy selection and processing. This paper describes IMS technology for both standard eutectic SnPb and Pb-free wafer bumping. Existing mainstream bumping technologies are also reviewed, with a focus on the challenges of new industry requirements. Early manufacturing challenges are addressed, including solutions that demonstrated the appropriateness of IMS technology for low-cost 300-mm Pb and Pb-free wafer bumping. Early process and reliability data are also reviewed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The evolution of build-up package technology and its design challenges

    Publication Year: 2005 , Page(s): 641 - 661
    Cited by:  Papers (12)  |  Patents (6)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (602 KB)  

    This paper reviews sequential build-up (SBU) laminate substrate development from its beginning in 1988 and reports on developments in this technology for IBM applications since its adoption in 2000. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for application-specific integrated circuit (ASIC) and microprocessor packaging applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effects of mechanical stress and moisture on packaging interfaces

    Publication Year: 2005 , Page(s): 663 - 675
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (497 KB)  

    When microelectronic packages fail in accelerated stress testing, it is often because of mechanical stress and/or moisture acting upon interfaces between polymeric adhesives or encapsulants and other package components such as solder interconnects, chip passivation, heat sinks, and chip carrier surfaces. Once the polymer loses adhesion, even if only in a small area, delamination at the interface can occur over time, leading to package failure. This paper describes an adhesion test methodology, using model materials and interfaces rather than actual packages, which has increased our understanding of the effects of mechanical stress and moisture and how they interact to induce adhesion failures. The effects of increasing severity of moisture exposures at elevated temperature and humidity conditions were measured using adhesion testing of epoxy/steel interfaces with and without adhesion promoters. An important aspect of this investigation pertained to the effect of the combination of mechanical stressing and exposure to moderate moisture conditions followed by solder reflow temperatures, again comparing the results for interfaces with and without adhesion promoters. Epoxy interfaces were weakened by the combination of mechanical stress and moisture exposure, thus allowing pockets of water to collect and cause delamination during subsequent solder reflows. Some insights are offered on how best to prevent this package failure mode, referred to as “popcorning,” caused by vaporization of moisture at the interface. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Latent defect screening for high-reliability glass-ceramic multichip module copper interconnects

    Publication Year: 2005 , Page(s): 677 - 685
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    Nonlinear electrical conduction effects arising from local heating provide a means for detecting the presence of latent defects that are at risk of becoming open electronic circuits under stress. A special choice of ac drive current results in a dc intermodulation signal produced by nonlinear conduction, and offers several practical advantages over previous techniques involving ac harmonics. A key feature is the use of digital signal processing to provide speed, accuracy, and flexibility of measurement. A manufacturing screening system involving an automated prober integrated with the defect-detection tool is used to test high-performance glass-ceramic substrate interconnects used in advanced microelectronic packaging. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-speed electrical testing of multichip ceramic modules

    Publication Year: 2005 , Page(s): 687 - 697
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (459 KB)  

    This paper reports on the successful application of very-high-performance robotics in the electrical testing of multichip modules using only two probes, breaking with the old traditional array of probes as the primary test method. Complete production line tools include two high-speed Hummingbird® probing robots and precise x-y tables to carry them and a fast, accurate opens-shorts test. To ensure fast probe placement without damaging the part under test requires real-time control hardware and software to operate with extreme precision, flexibility, and programmability to accommodate any part. Finally, because a module can have nearly 100,000 points to be probed, computing an optimal path for the two probes to take for full testing of a part can greatly reduce test time. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Mixing, rheology, and stability of highly filled thermal pastes

    Publication Year: 2005 , Page(s): 699 - 707
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (453 KB)  

    Thermal pastes play an important role in transmitting heat generated by an integrated circuit chip from its back side to a cooling cap or heat sink which transfers the heat to the environment. Most thermal pastes are formulations of solid, thermally conducting particles in a liquid matrix loaded to very high solids content. The mixing process for such pastes is complex but important, since it determines several of the paste properties. In particular, paste rheology is related to the work imparted to the paste during the mixing process. It determines the minimum bondline between solid surfaces that can be attained with a particular paste during the assembly process, which is essentially a squeeze flow process. Paste stability depends on the amount of entrapped air incorporated during the mixing process; this is demonstrated by infrared (IR) visualization of the degradation of air-containing paste in a computer-chip—heat-sink gap and the absence of this degradation mechanism in vacuum-mixed paste. This paper describes two different mixing processes for highly filled thermal pastes, the associated changes in their rheological behavior, and paste degradation in chip—heat-sink gaps during thermal stressing. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Challenges of data center thermal management

    Publication Year: 2005 , Page(s): 709 - 723
    Cited by:  Papers (15)  |  Patents (11)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    The need for more performance from computer equipment in data centers has driven the power consumed to levels that are straining thermal management in the centers. When the computer industry switched from bipolar to CMOS transistors in the early 1990s, low-power CMOS technology was expected to resolve all problems associated with power and heat. However, equipment power consumption with CMOS has been rising at a rapid rate during the past 10 years and has surpassed power consumption from equipment installed with the bipolar technologies 10 to 15 years ago. Data centers are being designed with 15–20-year life spans, and customers must know how to plan for the power and cooling within these data centers. This paper provides an overview of some of the ongoing work to operate within the thermal environment of a data center. Some of the factors that affect the environmental conditions of data-communication (datacom) equipment within a data center are described. Since high-density racks clustered within a data center are of most concern, measurements are presented along with the conditions necessary to meet the datacom equipment environmental requirements. A number of numerical modeling experiments have been performed in order to describe the governing thermo-fluid mechanisms, and an attempt is made to quantify these processes through performance metrics. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

    Publication Year: 2005 , Page(s): 725 - 753
    Cited by:  Papers (87)  |  Patents (17)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1478 KB)  

    System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a “virtual chip” using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Exploitation of optical interconnects in future server architectures

    Publication Year: 2005 , Page(s): 755 - 775
    Cited by:  Papers (110)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (780 KB)  

    Optical fiber links have become ubiquitous for links at the metropolitan and wide area distance scales, and have become common alternatives to electrical links in local area networks and cluster networks. As optical technology improves and link frequencies continue to increase, optical links will be increasingly considered for shorter, higher-bandwidth links such as I/O, memory, and system bus links. For these links closer to processors, issues such as packaging, power dissipation, and components cost assume increasing importance along with link bandwidth and link distance. Also, as optical links move steadily closer to the processors, we may see significant differences in how servers, particularly high-end servers, are designed and packaged to exploit the unique characteristics of optical interconnects. This paper reviews the various levels of a server interconnect hierarchy and the current status of optical interconnect technology for these different levels. The potential impacts of optical interconnect technology on future server designs are also reviewed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements

    Publication Year: 2005 , Page(s): 777 - 803
    Cited by:  Papers (8)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2264 KB)  

    Research on Rent's rule in electrical engineering, the applied sciences, and technology has been based on the publication of a 1971 interpretation of Rent's memoranda by B. S. Landman and R. L. Russo. Because of the wide impact of Rent's work and requests from researchers, we present his original memoranda in this paper. We review the impact of Rent's work and present the memoranda in the context of IBM computer hardware development since the 1950s. Furthermore, because computer hardware components have changed significantly since the memoranda were written in 1960, a new interpretation is needed for today's ultra-large-scale integrated circuitry. On the basis of our analysis of the memoranda, one of the authors' personal knowledge of the 1401 and 1410 computers, and our experience in the design of high-performance circuitry for microprocessor chips, we have derived an historically equivalent interpretation of Rent's memoranda that is suitable for today's computer components. We describe an application of our historically equivalent interpretation to the problem of assessing on-chip interconnection requirements of control logic circuitry in the IBM POWER4™ microprocessor. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center