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IBM Journal of Research and Development

Issue 6 • Date Nov. 2008

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Displaying Results 1 - 12 of 12
  • Preface

    Publication Year: 2008 , Page(s): 539 - 540
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (44 KB)  

    In future systems, continuing performance improvements, power efficiency, and smaller form factors for both portable product applications and fixed location products will be important. Take, for example, the billions of portable cell phones sold each year wherein the higher function products in this family seek increasing function with each generation while maintaining a fixed size. Another example is high-performance computing systems in which higher performance levels and high power efficiency are leading to high-bandwidth and low-latency multicore processors linked to ever higher stores of close proximity memory. View full abstract»

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  • Is 3D chip technology the next growth engine for performance improvement?

    Publication Year: 2008 , Page(s): 541 - 552
    Cited by:  Papers (41)  |  Patents (7)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (703 KB)  

    The semiconductor industry is reaching a fascinating confluence in several evolutionary trends that will likely lead to a number of revolutionary changes in how computer systems are designed, implemented, scaled, and used. Since Moore's Law, which has driven the evolution in systems for the last several decades, is imminently approaching real and severe limitations, the ability to create three-dimensional (3D) device stacks appears promising as a way to continue to integrate more devices into a “chip.” While on the one hand, this nascent ability to make “3D technology” can be interpreted as merely an extension of Moore's Law, on the other hand, the fact that systems can now be integrated across multiple planes poses some novel opportunities, as well as serious challenges and questions. In this paper, we explore these various challenges and opportunities and discuss structures and systems that are likely to be facilitated by 3D technology. We also describe the ways in which these systems are likely to change. Since 3D technology offers some different value propositions, we expect that some of the most important ways in which 3D technology will likely impact our approach to future systems design, implementation, and usage are not yet obvious to most system designers, and we outline several of them. View full abstract»

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  • Three-dimensional silicon integration

    Publication Year: 2008 , Page(s): 553 - 569
    Cited by:  Papers (131)  |  Patents (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1461 KB)  

    Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (<10/cm2 to 108/cm2), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems. View full abstract»

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  • Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

    Publication Year: 2008 , Page(s): 571 - 581
    Cited by:  Papers (36)  |  Patents (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (996 KB)  

    As traditional CMOS scaling becomes progressively more difficult and less beneficial to overall system performance, three-dimensional silicon integration technologies have begun to receive considerable attention. An advanced packaging solution based on a thin silicon carrier has been developed to provide interconnection between integrated circuits (ICs) and other devices at densities far beyond those of current first-level packaging. The silicon carrier employs fine-pitch Cu damascene wiring, high-density solder interconnections, and through-silicon vias (TSVs). A key enabling technology element is the TSV, which may be naturally scaled to provide vertical interconnection in stacked ICs as well as silicon carriers. In this paper, we discuss the evolution in both TSV design and process flow that has led to TSV technology which produces vias with resistances on the order of 10–20 mΩ and yields on the order of 99.99% at wafer level in a research laboratory environment. Two generalized process approaches to forming TSVs are discussed, the “vias-first” and the “vias-last” methods, along with related advantages and potential drawbacks of each. Improvement to these process flows and structures is afforded by simple changes of via geometry from cylindrical to annular or from annular to multibar. While various TSV metallurgies are reviewed, tungsten is shown to be a nearly optimal choice. Results on via resistance, electrical yield, and current-carrying capacity are covered. The use of electrical modeling to predict structures with superior electrical and mechanical properties is also described. View full abstract»

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  • Wafer-level 3D integration technology

    Publication Year: 2008 , Page(s): 583 - 597
    Cited by:  Papers (32)  |  Patents (6)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed. View full abstract»

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  • 3D chip stacking with C4 technology

    Publication Year: 2008 , Page(s): 599 - 609
    Cited by:  Papers (17)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1198 KB)  

    Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 µm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated. View full abstract»

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  • 3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

    Publication Year: 2008 , Page(s): 611 - 622
    Cited by:  Papers (40)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1050 KB)  

    Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 µm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ. View full abstract»

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  • Thermomechanical modeling of 3D electronic packages

    Publication Year: 2008 , Page(s): 623 - 634
    Cited by:  Papers (14)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (626 KB)  

    Development of complex electronic packages requires a judicious combination of experimentation and modeling. Fabrication costs of electronic packaging prototypes can be prohibitive; therefore, the building of effective virtual prototypes provides an important challenge for the modeling community. Fortunately, finite-element modeling (FEM) has become sufficiently mature to allow technologists to develop reliable insights into the thermal and mechanical integrity of proposed structures. For modeling to be leveraged as an effective means of avoiding thermally related mechanical problems, the diversity in size scale found in three-dimensional electronic packages must be carefully considered and addressed. Employing three distinct examples, we summarize our experience and insights in applying FEM in order to make informed decisions in the early stages of product package research and development. View full abstract»

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  • Through-silicon vias enable next-generation SiGe power amplifiers for wireless communications

    Publication Year: 2008 , Page(s): 635 - 648
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1262 KB)  

    We feature a 0.35-µm SiGe BiCMOS technology (SiGe 5PAe) that is optimized for power amplifier (PA) applications. The key feature of this technology is a novel low-inductance ground to the package using through-silicon vias (TSVs) that results in a competitive solution for future multiband and multimode PA integration. The tungsten-filled, multifinger, bar-shaped TSV delivers more than a 75% reduction in inductance compared to a traditional wirebond. This enables higher frequency applications with a roughly 20% reduction in die area without compromising the technology reliability for use conditions in a low-cost plastic QFN (quad flat no leads) package. In this paper we demonstrate the commercial feasibility of the TSV, its RF performance, its reliability, and its usefulness in a demanding WiMAX® (Worldwide Interoperability for Microwave Access) PA application. View full abstract»

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  • Author index for papers in Volume 52

    Publication Year: 2008 , Page(s): 649 - 656
    Save to Project icon | PDF file iconPDF (77 KB)  
    Freely Available from IEEE
  • Subject index for papers in Volume 52

    Publication Year: 2008 , Page(s): 657 - 661
    Save to Project icon | PDF file iconPDF (60 KB)  
    Freely Available from IEEE
  • Errata [Erratum]

    Publication Year: 2008 , Page(s): 663
    Save to Project icon | PDF file iconPDF (46 KB)  
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Aims & Scope

The IBM Journal of Research and Development is a peer-reviewed technical journal, published bimonthly, which features the work of authors in the science, technology and engineering of information systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Clifford A. Pickover
IBM T. J. Watson Research Center