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Circuits, Devices & Systems, IET

Issue 1 • Date January 2010

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Displaying Results 1 - 9 of 9
  • 1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom

    Page(s): 1 - 13
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1353 KB)  

    A low-voltage 1.2-V, 10-bit, 60-360 MS/s six channels time-interleaved reset-opamp pipelined ADC is designed and implemented in a 0.18-μm CMOS (V THN/V THP = 0.63=V/-0.65 V for mid-supply floating switches). Without using on-chip high-voltage and low-V T options, the proposed ADC employs low-voltage resistive-demultiplexing techniques, low-voltage gain-and-offset compensation, feedback current biasing to reduce the sensitivity of the bias current over process variations and current-mode sub-ADCs with static current sharing for a low-voltage time-interleaved implementation. Speed options of 60-360 MS/s are available with scalable power and they can be obtained by automatic selection of the number of time-interleaved channels. The chip measurement results show that the ADC exhibits a differential non-linearity (DNL)/integral non-linearity (INL) better than 0.9/1.2 LSB and a peak SNDR above 54 dB, for all speed options, while consuming 85 mW at 60 MS/s and 426 mW at 360 MS/s. The active die area is 13.2 mm2. View full abstract»

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  • A memory-free modified discrete cosine transform architecture for MPEG-2/4 AAC

    Page(s): 14 - 23
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (537 KB)  

    Most current audio coding standards use the modified discrete cosine transform (MDCT) to transform an audio sequence from the time domain into the frequency domain. Existing architectures for MDCT use a lookup table to store cosine values in read-only memory (ROM). For MPEG-2/4 AAC, the memory space taken up by the required lookup table makes the circuit implementation inflexible and large because of the long window length. Therefore this study proposes a memory-free architecture for MDCT without a lookup table. The proposed architecture adopts the arithmetic circuit module to calculate the cosine function based on the Taylor and Maclaurin series approximations and makes use of the symmetric and periodic identities of trigonometric functions to reduce circuit complexity. 0.18 m TSMC cell library technology is used to synthesise the proposed architecture, which requires about 9213 gates with a maximum operation frequency of 100 MHz. The proposed architecture, which has a flexible window length to perform MDCT, can be implemented in an area smaller than that of ROM-based architectures. View full abstract»

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  • V-band variable gain amplifier applying efficient design methodology with scalable transmission lines

    Page(s): 24 - 29
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    In this study, a 60 GHz variable gain low noise amplifier with more than 20 dB gain is presented. An efficient design methodology employing scalable transmission lines is applied, which can avoid iterative EM simulations and predict the circuit behaviour very accurately. Different transmission line modelling approaches are compared to each other, and a simple yet flexible model is eventually chosen. The circuit has been fabricated and measured on-wafer. The power consumption of only 7.3 mW is, to the knowledge of the authors, the lowest value reported for a V-band amplifier. View full abstract»

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  • Reduced complexity analogue-to-residue conversion employing folding number system

    Page(s): 30 - 41
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (876 KB)  

    Digital signal processing (DSP) algorithms are computationally intensive and require recursive multiplication and addition. Residue number systems (RNS) offer significant advantages over conventional number systems when used in the design of special purpose DSP architectures. However, conversion of analogue signals into their residue equivalents requires first converting the signal to binary equivalents and subsequently using modular circuits to convert the resultant binary to residues. A new number system called the folding number system (FNS) is proposed and used as the basis for residue conversion. Since FNS has one-to-one correspondence with RNS, the proposed method converts the analogue signal to its RNS equivalents using concealed symmetrical residues in FNS domain. The conversion is simple and uses analogue folding circuits, comparators and combinatorial logic circuits. High-frequency analogue signals can be efficiently converted thus enabling RNS to be implemented in high-speed signal processing architectures. View full abstract»

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  • High-performance simulator for digital audio class D amplifiers

    Page(s): 42 - 47
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (417 KB)  

    A new transient analysis simulator for digital class D amplifiers, which significantly reduces the simulation time (more than ten-fold), and which provides an accurate and robust audio performance analysis, is presented in this study. This simulator, called a hybrid simulator, is of special interest because it provides a better compromise between time and accuracy when compared with previous work. This simulator consists in keeping the most representative states of the transient simulation to process an optimal simulation. The results obtained by this new technique are compared with standard transient simulations (Eldo) and with experimental measurements. The circuit under test has been designed on 0.13 m CMOS technology and, an FPGA is used for digital modulator implementation. View full abstract»

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  • Filterless class D amplifiers: power-efficiency and power dissipation

    Page(s): 48 - 56
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (627 KB)  

    Filterless Class D amplifiers are based on the tri-state modulation architecture. In this study, the authors show that it is possible to employ the conventional Class D amplifier (that requires an LC output filter) as a filterless amplifier (hence not requiring the LC filter) if certain circuit conditions are satisfied - specifically a sufficiently high carrier frequency and a loudspeaker with sufficient inductance. As the high-frequency (beyond the audio range) components of the tri-state modulation and of the conventional modulation are dissipated in the loudspeaker, the rating of the loudspeaker would need to accommodate not only the audio signal power but also the power, P sw, due to the attenuation of the high-frequency components. By means of double-Fourier series analysis, the authors derive expressions for P sw and for power-efficiency of filterless Class D amplifiers based on the tri-state modulation and on the conventional modulation. These derived expressions provide meaningful insight into the design and application of these amplifiers, including practical means to improve their power-efficiency and the associated implications thereof. To determine the dissipation of the high-frequency components in the loudspeaker, the authors extend the well established loudspeaker model in the audio range to a high-frequency model, and the required added power rating of the loudspeaker is determined. The authors show, somewhat serendipitously, that if certain conditions are satisfied, the power-efficiency of the tri-state and the conventional filterless amplifiers are nearly comparable. The analyses herein are verified by experimental measurements. View full abstract»

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  • Switched positive/negative charge pump design using standard CMOS transistors

    Page(s): 57 - 66
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (601 KB)  

    The most common approach used in the generation of on-chip high voltages are based on Dickson's charge pump. In embedded and stand-alone designs of non-volatile memories, multiple charge pumps are utilised to generate both positive and negative voltages. Owing to high voltage drop across their terminals, high-voltage transistors are used to implement charge transfer function in many charge pump designs. The authors present a switchable charge pump design that utilises standard (low voltage) transistors to generate positive or negative high voltage based on the required mode of operation. Such design eliminates the need for multiple charge pumps, hence resulting in better utilisation of the available silicon area. Moreover, the use of standard transistors is shown to provide better performance/efficiency than designs that uses high-voltage transistors. View full abstract»

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  • Geometric centre tracking of tagged objects using a low power demodulation smart vision sensor

    Page(s): 67 - 77
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (953 KB)  

    In this study, a modulated light detecting smart CMOS image sensor is presented. The design has the ability to sense asynchronous signals transmitted from electronic markers such as flashing light emitting diodes (LEDs) tagged on moving objects. The geometric centre of the detected region is returned as the output result. With the presented sensor, object localisation and position detection functions are simplified, performed at higher speeds in real time and power requirement is reduced. The sensor in-pixel processing filters out the background image data, detects the modulated marker regions and projects the extracted region on the two axes, while the geometric centre extraction units placed at each axis identify the coordinates assigned to the marker. The design presents less sensitivity to object texture compared with techniques based on edge extraction or binarisation. The sensor has been designed as a 64 ?? 64 pixel VLSI CMOS chip in the 0.35 ??m standard CMOS technology and analysed in the presence of mismatches and noise. Issues such as sensor array scalability, speed and power dissipation are also examined in this study and features of the sensor are reported and compared with some previous designs. View full abstract»

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  • Current and voltage transfer function filters using a single active device

    Page(s): 78 - 86
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    In this study, current and voltage transfer function filters using single active component, namely, current backward transconductance amplifier (CBTA) are presented. The proposed structures are a single-input three outputs (SITO) current-transfer function filter, a single-input four-output (SIFO) voltage transfer function filter and three-input single-output (TISO) voltage transfer function filter. The proposed filters have low active and passive sensitivities and use canonical number of electronics components. The validity of the proposed circuits is demonstrated by PSPICE simulations and experimental results. Operation range of the CBTA and its parasitic effects are also discussed. View full abstract»

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Aims & Scope

IET Circuits, Devices & Systems covers circuit theory and design, circuit analysis and simulation, computer aided design,  filters, circuit implementations, cells and architectures for integration.

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