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IEEE Computer Architecture Letters

Issue 2 • Feb. 2009

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Displaying Results 1 - 18 of 18
  • [Front cover]

    Publication Year: 2009, Page(s): c1
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  • Editorial Board [Cover2]

    Publication Year: 2009, Page(s): c2
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  • Introducing the New Editor-in-Chief of IEEE Computer Architecture Letters

    Publication Year: 2009, Page(s):37 - 38
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  • Letter from the Editor

    Publication Year: 2009, Page(s): 39
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  • Exploiting locality to improve circuit-level timing speculation

    Publication Year: 2009, Page(s):40 - 43
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (98 KB) | HTML iconHTML

    Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins, eliminating power and performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. This work has not evaluated or exploited the disparity of error rates at the level of static instructions. In this paper, we... View full abstract»

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  • PRR-PRR Dynamic Relocation

    Publication Year: 2009, Page(s):44 - 47
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB) | HTML iconHTML

    Partial bitstream relocation (PBR) on FPGAs has been gaining attention in recent years as a potentially promising technique to scale parallelism of accelerator architectures at run time, enhance fault tolerance, etc. PBR techniques to date have focused on reading inactive bitstreams stored in memory, on-chip or off-chip, whose contents are generated for a specific partial reconfiguration region (P... View full abstract»

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  • Power Management of Datacenter Workloads Using Per-Core Power Gating

    Publication Year: 2009, Page(s):48 - 51
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB) | HTML iconHTML

    While modern processors offer a wide spectrum of software-controlled power modes, most datacenters only rely on dynamic voltage and frequency scaling (DVFS, a.k.a. P-states) to achieve energy efficiency. This paper argues that, in the case of datacenter workloads, DVFS is not the only option for processor power management. We make the case for per-core power gating (PCPG) as an additional power ma... View full abstract»

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  • A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors

    Publication Year: 2009, Page(s):52 - 55
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (439 KB) | HTML iconHTML

    Process variations in advanced nodes introduce significant core-to-core performance differences in single-chip multi-core architectures. Isolating each core with its own frequency and voltage island helps improving the performance of the multi-core architecture by operating at the highest frequency possible rather than operating all the cores at the frequency of the slowest core. However, inter-co... View full abstract»

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  • Characterizing the Energy Consumption of Software Transactional Memory

    Publication Year: 2009, Page(s):56 - 59
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB) | HTML iconHTML

    The well-known drawbacks imposed by lock-based synchronization have forced researchers to devise new alternatives for concurrent execution, of which transactional memory is a promising one. Extensive research has been carried out on software transaction memory (STM), most of all concentrated on program performance, leaving unattended other metrics of great importance like energy consumption. This ... View full abstract»

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  • Operand Registers and Explicit Operand Forwarding

    Publication Year: 2009, Page(s):60 - 63
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (122 KB) | HTML iconHTML

    Operand register files are small, inexpensive register files that are integrated with function units in the execute stage of the pipeline, effectively extending the pipeline operand registers into register files. Explicit operand forwarding lets software opportunistically orchestrate the routing of operands through the forwarding network to avoid writing ephemeral values to registers. Both mechani... View full abstract»

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  • Accurate Functional-First Multicore Simulators

    Publication Year: 2009, Page(s):64 - 67
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB) | HTML iconHTML

    Fast and accurate simulation of multicore systems requires a parallelized simulator. This paper describes a novel method to build cycle-accurate-capable and parallelizable functional-first simulators of multicore targets. View full abstract»

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  • [Advertisement]

    Publication Year: 2009, Page(s): 68
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  • [Advertisement]

    Publication Year: 2009, Page(s): 69
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  • [Advertisement]

    Publication Year: 2009, Page(s): 70
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  • [Advertisement]

    Publication Year: 2009, Page(s): 71
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  • [Advertisement]

    Publication Year: 2009, Page(s): 72
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  • Information for authors

    Publication Year: 2009, Page(s): c3
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  • IEEE Computer Society [Cover4]

    Publication Year: 2009, Page(s): c4
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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Daniel J. Sorin
Duke University
Electrical & Computer Engineering
PO Box 90291
Durham, NC 27708
e-mail: sorin@ee.duke.edu