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# IEEE Transactions on Circuits and Systems II: Express Briefs

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Displaying Results 1 - 23 of 23

Publication Year: 2009, Page(s): C1
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2009, Page(s): C2
| PDF (39 KB)
• ### Fractional-$N$ Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial

Publication Year: 2009, Page(s):881 - 885
Cited by:  Papers (18)
| | PDF (224 KB) | HTML

The fundamentals and state of the art in fractional-N phase-locked-loop (PLL)-based frequency synthesis are reviewed. Particular emphasis is placed on delta-sigma fractional-N PLLs and quantization noise and fractional spur suppression techniques for wide-bandwidth applications. View full abstract»

• ### Parameter Derivation of Type-2 Discrete-Time Phase-Locked Loops Containing Feedback Delays

Publication Year: 2009, Page(s):886 - 890
Cited by:  Papers (6)
| | PDF (245 KB) | HTML

Modern implementations of discrete-time phase-locked loops (DT-PLLs) often contain delayed feedback. The delays are usually a side effect to pipelining, filtering, or other inner-loop mechanisms. Each delay increases the order of the system by introducing an additional pole to the closed-loop transfer function and, in many cases, makes the traditional type-2 loop equations obsolete. This brief des... View full abstract»

• ### A 405-nW CMOS Temperature Sensor Based on Linear MOS Operation

Publication Year: 2009, Page(s):891 - 895
Cited by:  Papers (37)  |  Patents (1)
| | PDF (343 KB) | HTML

This brief presents a CMOS temperature sensor suitable for ultralow-power applications. With a MOS transistor operating in the linear region, a linear relationship between delay and temperature can be obtained. A differential sensing architecture is utilized to reduce the signal offset and increase the effective signal-to-noise ratio. A design methodology concerning power optimization and improved... View full abstract»

• ### Design Constraints for Image-Reject Frequency-Translating $DeltaSigma$ Modulators

Publication Year: 2009, Page(s):896 - 900
Cited by:  Papers (2)  |  Patents (1)
| | PDF (401 KB) | HTML

This brief derives design constraints for bandpass ΔΣ modulators that use mixers to perform frequency downconversion inside their ΔΣ loop. Such systems, which are referred to as frequency-translating ΔΣ modulators, facilitate direct analog-to-digital conversion (ADC) of high-frequency signals that cannot adequately be processed using classical bandpa... View full abstract»

• ### Adaptive Predistortion Using a $DeltaSigma$ Modulator for Automatic Inversion of Power Amplifier Nonlinearity

Publication Year: 2009, Page(s):901 - 905
Cited by:  Papers (6)
| | PDF (544 KB) | HTML

This brief demonstrates a new adaptive digital predistortion architecture particularly suited to mobile handset applications. The central idea is to build a lookup table (LUT) that directly captures the static compressive nonlinearity of the power amplifier (PA) and then insert this LUT into the feedback path of a ΔΣ modulator. The oversampled ΔΣ modulator au... View full abstract»

• ### Numerical Dynamic Characterization of Peak Current-Mode-Controlled DC–DC Converters

Publication Year: 2009, Page(s):906 - 910
Cited by:  Papers (10)
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Peak current-mode (PCM) control of pulsewidth-modulated (PWM) dc-dc converters is highly desired for its fast dynamic response and automatic overload protection. Dynamic characterization of PCM converters is mainly conducted via average-value modeling. However, deriving the average-value models of PCM converters is challenging when the component parasitics and different conduction modes are consid... View full abstract»

• ### Experimental Validation of SPICE Modeling Diffraction Effects in a Pulse–Echo Ultrasonic System

Publication Year: 2009, Page(s):911 - 915
Cited by:  Papers (4)
| | PDF (208 KB) | HTML

During its propagation in a given medium, the ultrasonic wave is disturbed by several phenomena that affect the waveform in both time and frequency domains. Among these phenomena, the most important are absorption, nonlinearity, and diffraction. The aim of this brief is to simulate in the SPICE-like simulator the diffraction losses in a pulse-echo ultrasonic system. A set of Gaussian beams is used... View full abstract»

• ### Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines

Publication Year: 2009, Page(s):916 - 920
Cited by:  Papers (5)
| | PDF (673 KB) | HTML

A new discrete wavelet transform (DWT) architecture is proposed to realize a memory-efficient 2-D DWT processor. The proposed DWT processor conforms to dual-line scanning to remove the transpose buffer. In the previous single-line DWT architectures, the transpose buffer size is proportional to the row size of the image. The conventional dual-line DWT architecture is constructed by using the convol... View full abstract»

• ### Low Computational Complexity, Low Power, and Low Area Design for the Implementation of Recursive DFT and IDFT Algorithms

Publication Year: 2009, Page(s):921 - 925
Cited by:  Papers (18)
| | PDF (435 KB) | HTML

A novel recursive algorithm for discrete Fourier transform (DFT) and its inverse transform (IDFT) is proposed in this brief. It was found that the proposed algorithm and its implementation outperformed other existing recursive algorithms. The proposed algorithm was found to 1) reduce multiplication computations by 50.5% using the symmetric identity of coefficients and a resource-sharing technique ... View full abstract»

• ### Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage

Publication Year: 2009, Page(s):926 - 930
Cited by:  Papers (10)
| | PDF (704 KB) | HTML

A novel power gating (PG) structure using only low-threshold-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed to extend the PG to an ultralow-voltage region ( ~ 0.3 V). The proposed structure deploys series-connected low-V th footers with two virtual ground ports and selectively chooses the logic cells for connecting them to each virtual ground por... View full abstract»

• ### A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications

Publication Year: 2009, Page(s):931 - 935
Cited by:  Papers (28)
| | PDF (539 KB) | HTML

In this brief, we propose a lower error and ROM-free logarithmic converter. The proposed converter can lead to area-efficient hardware implementation as it avoids the need for a ROM by employing simple computation units for logarithmic approximation. Our proposed logarithmic conversion algorithm partitions the exact logarithmic curve into two symmetric regions such that the slopes in the two regio... View full abstract»

• ### On the Transfer Function Error of State-Space Filters in Fixed-Point Context

Publication Year: 2009, Page(s):936 - 940
Cited by:  Papers (6)
| | PDF (178 KB) | HTML

This brief presents a new measure used for the implementation of filters/controllers in state-space form. It investigates the transfer function deviation generated by the coefficient quantization. The classical L 2-sensitivity measure is extended with precise consideration on their fixed-point representation in order to make a more valid measure. By solving the related optimal re... View full abstract»

• ### Equiripple Approximation of Half-Band FIR Filters

Publication Year: 2009, Page(s):941 - 945
Cited by:  Papers (4)
| | PDF (836 KB) | HTML

A novel design procedure of equiripple (ER) half-band (HB) finite-impulse-response (FIR) filters is developed. A solution to the approximation problem in terms of generating function and zero-phase transfer function for the ER HB FIR filter is presented. The ER HB FIR filters are optimal in the Chebyshev sense. The closed-form solution provides an efficient computation of the impulse response of t... View full abstract»

• ### SPICE Behavioral Model of the Tunneling Field-Effect Transistor for Circuit Simulation

Publication Year: 2009, Page(s):946 - 950
Cited by:  Papers (12)
| | PDF (237 KB) | HTML

The tunneling field-effect transistor (TFET) is an alternative device for deep-submicrometer CMOS with very good short channel and leakage characteristics. In this brief, a SPICE behavioral model that well captures the I- V characteristics and the parasitic capacitance of the n-channel TFET is proposed to facilitate efficient circuit design and simulation. The validity of the model is verified wit... View full abstract»

• ### 2009 List of Reviewers

Publication Year: 2009, Page(s):951 - 955
| PDF (42 KB)
• ### ISCAS 2010 nono-bio circuit fabrics and systems

Publication Year: 2009, Page(s): 956
| PDF (642 KB)

Publication Year: 2009, Page(s): 957
| PDF (205 KB)
• ### IEEE 2009 Membership Application

Publication Year: 2009, Page(s):958 - 959
| PDF (1212 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

Publication Year: 2009, Page(s): 960
| PDF (33 KB)
• ### IEEE Circuits and Systems Society Information

Publication Year: 2009, Page(s): C3
| PDF (33 KB)
• ### Blank page [back cover]

Publication Year: 2009, Page(s): C4
| PDF (5 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org