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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 12 • Date Dec. 2009

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Displaying Results 1 - 25 of 25
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): C2
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  • Editorial: A Few Comments Before Leaving the Helm

    Page(s): 2529 - 2532
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  • A Low-Offset Low-Noise Sigma-Delta Modulator With Pseudorandom Chopper-Stabilization Technique

    Page(s): 2533 - 2543
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    This paper presents a low-offset low-noise sigma-delta modulator with pseudorandom chopper-stabilization technique. The comparison of the noise-cancellation ability with the correlated double sampling and chopper-stabilization techniques is demonstrated; also, the noise performance of these cancellation techniques is observed and discussed. Using the proposed technique, the modulator achieves 92 dB of dynamic range and -135 dB of noise floor while consuming 950 ??W from a 3-V supply. Based on the experimental results, the pseudorandom chopper-stabilization technique has a DC offset voltage that is 6 dB lower than that of the chopper-stabilization technique, and retains a thermal noise floor that is 1.6 dB lower than that of the correlated double sampling technique. View full abstract»

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  • Design Optimization of On-Chip Inductive Peaking Structures for 0.13- \mu{\hbox {m}} CMOS 40-Gb/s Transmitter Circuits

    Page(s): 2544 - 2555
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    This paper describes design methodologies for the optimal inductive peaking structures used for the 40-Gb/s serializing transmitter circuits presented in. The implemented transmitter had more than 400 on-chip inductors and transformers in order to achieve the bandwidth required for the 38.4-Gb/s operation demonstrated in a 0.13-μm CMOS process. A bridged T-coil network with inverted mutual coupling was found more effective than the conventional T-coil with sizeable driver-side capacitance. An iterative refinement procedure that directly optimizes the circuit's large-signal transient response at the presence of the inductor parasitics and device nonlinearities via HSPICE-ASITIC joint-simulation is described. The procedure resulted in more than 3 ?? improvement in bandwidth for the CML buffer, multiplexer, and latch circuits. It is shown that the area and the achievable bandwidth of the optimal inductive peaking structures will scale favorably with the CMOS technology trends. View full abstract»

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  • Second-Order Intermodulation in Current-Commutating Passive FET Mixers

    Page(s): 2556 - 2568
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    Amplitude-modulation detection in the mixer plagues the performance of the zero-intermediate-frequency receiver by downconverting the envelope of amplitude modulated blockers to baseband where the desired channel is after downconversion. Simple equations based on physical mechanisms of second-order intermodulation generation have been derived which can predict the IIP2 of the current-driven passive mixer accurately. Derived equations have been verified by SPECTRE and SPECTRE-RF simulations, and mixer optimization has been explained. View full abstract»

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  • Settling Time Optimization for Three-Stage CMOS Amplifier Topologies

    Page(s): 2569 - 2582
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    A new settling-time-oriented design methodology for the most common three-stage operational amplifier (op-amp) schemes reported in the literature is presented in this paper. The proposed approach allows the systematic sizing of the compensation network in order to reach the best closed-loop op-amp settling behavior. To demonstrate the effectiveness of the methodology and the correctness of the analysis, the examined three-stage op-amp topologies are designed in a commercial 0.35-??m CMOS technology. Circuit simulations show that the proposed design approach, for each investigated topology, guarantees a significant settling time reduction with respect to the compensation network sizing strategies proposed in the past. An ad-hoc figure of merit, which evaluates the trade-off between the settling time, the load capacitance and the total op-amp stage transconductances, is also defined in order to estimate the op-amp efficiency in terms of time-domain performances. View full abstract»

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  • A Biomedical Implantable FES Battery-Powered Micro-Stimulator

    Page(s): 2583 - 2596
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    The integrated circuit (IC) designs of an implantable functional electrical stimulation (FES) battery-powered micro-stimulator are presented in this paper. The battery is recharged by receiving power magnetically through a coil under supervision of a power management unit. To limit the heat generation on the stimulator when a large magnetic field is present, an on-chip rectifier is capable of limiting the induced voltage and reducing heat generation by providing a low impedance path. The same coil is also used for generating and receiving magnetic fields such that the distances among 16 different stimulator pairs can be estimated simultaneously. To facilitate different clinical applications, a bio-potential sensor is also included. The micro-stimulator can output mono-phasic stimulation current from an 8-bit exponential digital to analog converter (DAC) that has a range between ~2.5 ??A and ~10 mA. The stimulator communicates with an external master control unit through a 400-MHz wireless link that can support a bit rate of 2.486 MB/s in high speed mode. The total number of stimulators that the communication system can support is 852. View full abstract»

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  • An Analog Gabor Transform Using Sub-Threshold 180-nm CMOS Devices

    Page(s): 2597 - 2608
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    The Gabor transform can be used to represent a signal in terms of a set of pseudo basis functions, allowing a signal to be split into parallel paths of a lower bandwidth. An analog Gabor transform using sub-threshold CMOS continuous time filters designed from time domain impulse responses is described. A novel method for designing low power gm-C filters using simple models of identical transconductors is used to specify the transistor sizes. Measured results show that the transform consumes 7 ??W for an input signal bandwidth of 4 kHz, making it suitable for ultra low power systems. View full abstract»

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  • Hardware Implementation of {\rm GF}(2^{m}) LDPC Decoders

    Page(s): 2609 - 2620
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    Low density parity check (LDPC) codes over GF(2m) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2m) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2m) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2m) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes. View full abstract»

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  • Design of Extrapolated Impulse Response FIR Filters With Residual Compensation in Subexpression Space

    Page(s): 2621 - 2633
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    In this paper, an extrapolated impulse response filter with residual compensation is proposed for the design of discrete coefficient finite-impulse response (FIR) filters using subexpression sharing. The proposed technique utilizes the quasi-periodic nature of the filter impulse response to approximate the filter coefficients. The reduced degree of freedom of filter coefficients due to the quasi-periodic approximation is perfectly restored by introducing a residual compensation technique. The resulting subexpression sharing synthesis of discrete coefficient FIR filters has lower complexities than that of the conventional synthesis techniques in terms of number of adders. To further reduce the synthesis complexity, filter coefficients and residuals may be optimized in subexpression spaces. Mixed integer linear programming is formulated for the optimization. Numerical examples show that the number of adders required by synthesizing the filters in the proposed structure is significantly reduced compared to that of the conventional synthesis schemes synthesized in direct or transposed direct form. View full abstract»

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  • A Pipelined FFT Architecture for Real-Valued Signals

    Page(s): 2634 - 2643
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    This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency. The architecture is based on a novel algorithm for the computation of the RFFT, which, contrary to previous approaches, presents a regular geometry suitable for the implementation of hardware structures. Moreover, the algorithm can be used for both the decimation in time (DIT) and decimation in frequency (DIF) decompositions of the RFFT and requires the lowest number of operations reported for radix 2. Finally, as in previous works, when calculating the RFFT the output samples are obtained in a scrambled order. The problem of reordering these samples is solved in this paper and a pipelined circuit that performs this reordering is proposed. View full abstract»

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  • Two-Channel Quincunx QMF Banks Using Two-Dimensional Digital Allpass Filters

    Page(s): 2644 - 2654
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    This paper presents a novel structure for the analysis and synthesis filters of two-channel quincunx quadrature mirror filter (QQMF) banks. This structure uses an appropriate combination of 2-D recursive digital allpass filters (DAFs) with symmetric half-plane (SHP) support regions. The proposed analysis/synthesis filters possess a 2-D doubly complementary half-band (DC-HB) property that facilitates the design and implementation of the proposed two-channel QQMF banks. Moreover, the proposed structure provides approximately linear-phase response without magnitude distortion. The design problem of the proposed QQMF banks is appropriately formulated to result in a linear optimization problem that only minimizes the linear-phase error associated with the 2-D SHP DAFs in the p th-norm (Lp) sense. Efficient design techniques are developed to solve the Lp optimization problem for finding the coefficients of the 2-D recursive SHP DAFs. Finally, we provide simulation results for illustration and comparison. View full abstract»

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  • An Optimization Approach to Single-Bit Quantization

    Page(s): 2655 - 2668
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    This paper presents an optimization approach to single-bit quantization. The paper starts by redefining single-bit quantization as a maximum-likelihood sequence detection problem and by showing that the Viterbi algorithm is its optimal solution. It also shows that the conventional ???? converter implements a greedy solution to the same optimization problem. There is, moreover, a continuum of solutions with different degrees of complexity between the ????s and the Viterbi solution. The paper details one such intermediate-complexity solution (based on the M-algorithm) and demonstrates that with an appropriate noise shaping filter it achieves a performance very close to the optimal Viterbi solution. The paper concludes by presenting two procedures for designing effective noise shaping filters. View full abstract»

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  • Closed-Form Analytical Equations for Amplitude and Frequency of High-Frequency CMOS Ring Oscillators

    Page(s): 2669 - 2677
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    New closed-form equations are proposed for frequency and amplitude of a ring oscillator. The method is general enough to be used for all types of delay stages. Using exact large-signal circuit analysis, closed-form equations for estimating the frequency and amplitude of a ring oscillator are derived as an example. The method takes into account the effect of various parasitic capacitors to have better accuracy. The validity of the resulted equations is verified through simulations using TSMC 0.18 ??m CMOS process. Simulation results show the better accuracy of the proposed method compared with others. View full abstract»

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  • Energy Efficiency of Pulsed Actuations on Linear Resonators

    Page(s): 2678 - 2688
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    The objective of this paper is to show that under some circumstances, the sign of a sampled sinusoid sequences, briefly S 3, is optimal to provide maximum energy transfer to linear resonators in the context of discrete-time pulsed actuation at periodic times with bounded sequences. It will be proven that there is an optimal S 3 sequence which maximizes the resonator amplitude at any given finite time, and that under some conditions, there is a sufficiently high time above which any S 3 sequence at the resonant frequency of the resonator also provides a locally unique maximum, in the case of a lossless or leaky resonator. The tool used to prove this last result is a theorem of quadratic programming. Since pulsed digital oscillators (PDOs) under certain conditions produce S 3 sequences, a variation of the standard PDO topology that simplifies these conditions is also proposed. It is proved that except for a set of initial conditions of the resonator of zero Lebesgue measure, the bitstream at the output of this topology produces a locally unique maximum in the total energy transferred to the resonator. View full abstract»

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  • Global Uniform Synchronization With Estimated Error Under Transmission Channel Noise

    Page(s): 2689 - 2702
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    This paper investigates the problem of estimating synchronization errors and its application to global uniform synchronization with an estimated error bound for the master-slave chaos synchronization scheme via linear control input, which is possibly subject to disturbances by unknown but bounded channel noise and time-delay. Based on Lyapunov function, Razumikhin technique, nonlinear parametric variation, and input-to-state stability (ISS) theory, estimation formulas of synchronization errors with or without time-delays but with noise in transmission channel (TC) are derived. By using the error estimation formula, the maximal upper bound for time-delays is also obtained. These formulas can be used to design a control gain matrix which forces the synchronization error to the minimal value. Meanwhile, theoretical discussion is made by comparing Lyapunov-Krasovskii function method with respect to time-delays in TC. After the theoretical analysis, some representative examples and their numerical simulations are given for illustration. View full abstract»

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  • Adaptive Observers With Persistency of Excitation for Synchronization of Chaotic Systems

    Page(s): 2703 - 2716
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    We address the problem of master-slave synchronization of chaotic systems under parameter uncertainty and with partial measurements. Our approach is based on observer-design theory hence, we view the master dynamics as a system of differential equations with a state and a measurable output and we design an observer (tantamount to the slave system) which reconstructs the dynamic behavior of the master. The main technical condition that we impose is persistency of excitation (PE), a property well studied in the adaptive control literature. In the case of unknown parameters and partial measurements we show that synchronization is achievable in a practical sense, that is, with ??small?? error. We also illustrate our methods on particular examples of chaotic oscillators such as the Lorenz and the Lu oscillators. Theoretical proofs are provided based on recent results on stability theory for time-varying systems. View full abstract»

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  • An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits

    Page(s): 2717 - 2727
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    This paper describes a very-high-speed integrated-circuit hardware description language (VHDL)-based analog-node model, an associated driver component for the mixed-signal event-driven (MixED) simulation technique, and some primitive device models applied to radio-frequency integrated circuits. With the presented MixED method, analog circuits are modeled as a composition of controlled sources. Unlike other VHDL-based analog simulation methods, these MixED sources compute not only a real number representing an output voltage but also an output impedance. This allows the outputs of several MiXED sources to be connected in order to drive the same node signal n . The voltage of this record-type signal is automatically computed at its element n.u by resolution functions in compliance with Kirchhoff's current law. The data structure of the node signal n, its self-defined resolution functions, and an associated driver component are presented and discussed to meet different simulation requirements, such as speed, versatility, current accuracy, and adaptive time stepping. Several examples demonstrate how to behaviorally model mixed-signal components with this method with an emphasis on the simulation of a heterodyne receiver. Simulation speeds are compared to VHDL-AMS tools. View full abstract»

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  • A Calibrated Phase and Amplitude Control System for a 1.9 GHz Phased-Array Transmitter Element

    Page(s): 2728 - 2737
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    A system is proposed to allow the phase and amplitude of a signal to be accurately set and regulated over process and power supply variations. It uses a variable gain amplifier (VGA) in conjunction with the phase shifter to compensate for the variable losses of the phase shifter and simultaneously provide a means of adjusting the amplitude of the signal. The system has been fabricated in a 0.18 ??m CMOS process, and operates at 1.9 GHz. The phase can be set with 5 bits of control over a 240?? range and the amplitude can be varied over a 20 dB range. The feedback loops reduce the variation in |S 21| across the phase control range from 12.1 to 0.4 dB. For a changing power supply voltage the feedback loops reduce the maximum phase deviation from 28?? to 7?? , and across different test chips the maximum standard deviation over the phase control range is reduced from 12?? to 3??. View full abstract»

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  • A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion

    Page(s): 2738 - 2748
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    A technique of time-to-digital conversion is utilized in a digital demodulator for a low-power 2.4-GHz CMOS GFSK transceiver. The proposed time-to-digital converter (TDC) employs a self-sampling technique and an auto-calibration algorithm to avoid edge synchronization problems and the need of a delay-locked loop (DLL). With the TDC, a limiter and a digital demodulator can be employed simultaneously in the receiver to achieve low power consumption and high performance. Additionally, in the transmitter, the open-loop VCO modulation is adopted to save hardware and power consumption. The transmitter frequency drift in open-loop modulation and frequency offset between the receiver and the transmitter can be easily resolved by the proposed receiver architecture. All required building blocks of the proposed transceiver, except a RF matching network and a crystal, were implemented on a 4-mm2 chip by a 0.18-??m CMOS process. The receiver achieves -89 -dBm sensitivity at 0.1% BER with 1-Mb/s data rate, and the transmitter delivers up to 0-dBm output power. The receiver and transmitter consume 13.3 mA and 10.7 mA, respectively, from a 1.8-V power supply. View full abstract»

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  • Analysis and Design of an Adaptive-Step-Size Digital Controller for Switching Frequency Autotuning

    Page(s): 2749 - 2759
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    An adaptive-step-size autotuning algorithm and controller for power converters' switching frequency optimization with improved convergence performance is presented in this paper. The controller automatically tracks and determines the switching frequency of a power converter in order to achieve the highest power conversion efficiency under variable operating conditions including temperature variation effects, component aging effects, component's manufacturing process differences, input voltage changes and load current changes. The adaptive-step-size function results in improved adaptive controller convergence speed, convergences error and stability. In this paper, the proposed autotuning control loop for a power converter is theoretically analyzed and its design and stability criteria are developed. The developed algorithm operation is verified by experimental results obtained from a proof of concept prototype. View full abstract»

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  • ISCAS 2010

    Page(s): 2760
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  • 2009 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 56

    Page(s): 2761 - 2792
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    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Page(s): C3
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    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras