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Circuits, Devices & Systems, IET

Issue 6 • Date December 2009

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Displaying Results 1 - 8 of 8
  • Low-power split-path data-driven dynamic logic

    Page(s): 303 - 312
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (854 KB)  

    Data-pre-charged dynamic logic, also known as data-driven dynamic logic (D3L), is very efficient when low-power constraints are mandatory. Differently from conventional dynamic domino logic, which exploits a clock signal, D3L uses a subset of the input data signals for pre-charging the dynamic node, thus avoiding the clock distribution network. Power consumption is significantly reduced, but the pre-charge propagation path delay affects the speed performances and limits the energy-delay product (EDP) improvements. This study presents a new dynamic logic named split-path D3L (SPD3L) that overcomes the speed limitations of D3L. When applied to a 16 times 16 bit booth multiplier realised with STMicroelectronics 65 nm IV CMOS technology, the proposed technique leads to an EDP 25 and 30% lower than standard dynamic domino logic and conventional D3L counterparts, respectively. View full abstract»

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  • 24-GHz ultra-wideband transmitter for vehicular short-range radar applications

    Page(s): 313 - 321
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    This paper presents a 24-GHz transmitter for ultra-wideband short-range radar applications fabricated in a 0.13-mum SiGe:C BiCMOS technology. The circuit is composed of a frequency synthesiser, based on 24-GHz voltage-controlled oscillator in an N-integer phase-locked loop (PLL), a RF switch delivering a 0-dBm output power, and a tunable rectangular pulse generator, whose pulse width covers a range between 0.5 and 1.2 ns. The transmitter has been developed for a flip-chip bumping assembly on a module with an UWB antenna. Assuming a 10.5-dBi antenna gain, it is compliant with European Telecommunications Standards Institute (ETSI) transmission mask and is able to cover the main automotive applications addressing both a resolution better than 0.1 m and maximum unambiguous range of 15 m. View full abstract»

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  • Small signal analysis of quadrature LC oscillator operating at 59-62.5 GHz

    Page(s): 322 - 330
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (555 KB)  

    In this study, a comprehensive small signal analysis method for quadrature oscillators based on cross-coupled LC-tuned oscillators and parallel coupling is proposed. The analysis is suitable for circuits operating up to millimetre wave frequencies since the key parasitics of all circuit elements such as core amplifiers, coupling amplifiers, buffers, inductors and varactors are considered. This allows for efficient circuit and device optimisations. The proposed method is based on the consequent parallelisation of all individual network elements into a simple overall equivalent RLC tank. The analysis is employed for CMOS but can also be adapted to other technologies. To verify the analysis, a circuit with oscillation frequency around 61 GHz was designed in 90 nm silicon on insulator (SOI) CMOS. Frequency control is enabled by adjusting the gain in the feedback amplifiers. Hence, no lossy varactors are necessary. At 50 terminations, a supply voltage of 1.5 V and a total supply current of less than 56 mA, a tuning range above 3 GHz, an output power per channel of 19 dBm 1.5 dB and a phase noise of better than 80 dBc/Hz at 2 MHz offset are measured. View full abstract»

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  • Design of X-band complementary metal-oxide semiconductor-based frequency-modulation continuous-wave sensor

    Page(s): 331 - 339
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (810 KB)  

    This study presents an X-band complementary metal-oxide semiconductor-based frequency-modulation continuous-wave (FMCW) sensor system for transportation management. The proposed sensor system has two antennas, one to transmit signals and the other to receive them. The complete radio frequency (RF) transceiver is based on standard 0.18 m one-poly six-metal (1P6M) CMOS technology with a chip area of 1.68 mm 1.6 mm. Two planar leaky-mode antenna arrays with a gain of 18 dB are also designed. Experimental results indicate that the isolation between two antenna arrays that are 5.0 mm apart exceeds 42.0 dB at 10.5 GHz. The prototype of the FMCW sensor system is used in the range measurement of multiple lanes for the transportation management system (TMS). The major contribution of this study is that it integrates a 0.18 m CMOS transceiver and antenna arrays into an FMCW RF front end, and employs an IF amplifier and a digital signal processor to demonstrate that the beat frequencies are linear. Measurements made in field tests agree closely with the simulation results. View full abstract»

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  • Comparison of 24 GHz receiver front-ends using active and passive mixers in CMOS

    Page(s): 340 - 349
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (733 KB)  

    This study compares the key parameters of two integrated receiver front-end architectures: low noise amplifier (LNA) with active mixer against LNA with passive mixer. The authors discuss the differences in the performance and their impact on system characteristics for radar applications. A low-IF down-conversion receiver implementation is considered. The results are compared in measurement for two 24 GHz receiver front-end chips realised in a 0.13 mum digital CMOS process. Both circuits have been characterised over automotive temperature range -40 to 125degC. The front-end with an active mixer offers lower LO power dependence and exhibits better temperature stability, whereas the front-end with a passive mixer has the advantage of better input-referred linearity and lower flicker noise. View full abstract»

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  • A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS

    Page(s): 350 - 358
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (943 KB)  

    In the nanoscale CMOS process, the problem of leakage current causes the performance of the analog circuits to degrade. The leakage current of a loop filter, which is realised by MOS capacitors, significantly degrades the jitter performance of a phase-locked loop. A leakage suppression circuit is presented by using a combination of switchable varactors and current sources to compensate the leakage of MOS capacitors in a loop filter. This PLL has been fabricated in a 65 nm CMOS process and the core area is 0.4 0.5 mm2. With the leakage suppression circuit, the peak-to-peak jitter and the RMS jitter are 43 and 5.36 ps, respectively. The power is 17 mW for a 1.2 V supply. View full abstract»

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  • Distortion analysis of bootstrap switch using volterra series

    Page(s): 359 - 364
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (290 KB)  

    Linear behaviour of bootstrap switches is of critical importance in low-voltage analogue circuits and understanding the major factors affecting the linearity helps design a better switch. This study presents a theoretical approach for evaluating the distortion of bootstrap switches in the frequency domain based on the Volterra series. Five major factors affecting the linearity of the bootstrap switch are examined. In order to obtain a general design guideline the analysis is done in two parts. First, the distortion because of the non-linear I-V characteristic of the main transistor of the switch is considered. In the second part, the distortion because of sampling errors, such as clock feed-through and charge injection, are added to the analysis. The theoretical results are verified by circuit simulations in a 0.18 mum CMOS process, using HSpice. View full abstract»

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  • 5 GHz low power frequency synthesiser with dual-modulus counter

    Page(s): 365 - 375
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1083 KB)  

    A 5 GHz low power frequency synthesiser with a dual-modulus counter (DMC) was fabricated in 0.18 m CMOS technology. The DMC allows to reduce the power consumption and to provide the functionality of the divider without a swallower counter. The settling time takes no more than 5 s with an adaptive bandwidth topology. The measured phase noise is 87 dBc/Hz and 119 dBc/Hz at 10 kHz and 1 MHz offset frequencies, respectively. The reference spurs level is lower than 55 dBc at 10 MHz offset. The proposed synthesiser covers frequencies between 5.14 and 5.86 GHz in steps of 20 MHz and consumes 16.4 mW at 1.5 V supply voltage. View full abstract»

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Aims & Scope

IET Circuits, Devices & Systems covers circuit theory and design, circuit analysis and simulation, computer aided design,  filters, circuit implementations, cells and architectures for integration.

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