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IEEE Transactions on Computers

Issue 1 • Date Jan. 2010

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Displaying Results 1 - 19 of 19
  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2010, Page(s): c2
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  • A Novel Weighted-Graph-Based Grouping Algorithm for Metadata Prefetching

    Publication Year: 2010, Page(s):1 - 15
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3449 KB) | HTML iconHTML

    Although data prefetching algorithms have been extensively studied for years, there is no counterpart research done for metadata access performance. Existing data prefetching algorithms, either lack of emphasis on group prefetching, or bearing a high level of computational complexity, do not work well with metadata prefetching cases. Therefore, an efficient, accurate, and distributed metadata-orie... View full abstract»

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  • Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs

    Publication Year: 2010, Page(s):16 - 28
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4445 KB) | HTML iconHTML

    Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processing cores on the same chip. Chip multiprocessors (CMPs) constitute a good alternative to traditional monolithic designs for several reasons, among others, better levels of performance, scalability, and performance/energy ratio. On the other hand, higher clock frequen... View full abstract»

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  • Network-on-Chip Hardware Accelerators for Biological Sequence Alignment

    Publication Year: 2010, Page(s):29 - 41
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3366 KB) | HTML iconHTML

    The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially growing sequence databases, computing this operation at a large-scale is becoming expensive. An effective approach to speed up this operation is to integrate a very high number of processing elements in a single chip so tha... View full abstract»

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  • Communication-Aware Load Balancing for Parallel Applications on Clusters

    Publication Year: 2010, Page(s):42 - 52
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2455 KB) | HTML iconHTML

    Cluster computing has emerged as a primary and cost-effective platform for running parallel applications, including communication-intensive applications that transfer a large amount of data among the nodes of a cluster via the interconnection network. Conventional load balancers have proven effective in increasing the utilization of CPU, memory, and disk I/O resources in a cluster. However, most o... View full abstract»

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  • Improving Flash Wear-Leveling by Proactively Moving Static Data

    Publication Year: 2010, Page(s):53 - 65
    Cited by:  Papers (36)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4500 KB) | HTML iconHTML

    Motivated by the strong demand for flash memory with enhanced reliability, this work attempts to achieve improved flash-memory endurance without substantially increasing overhead and without excessively modifying popular implementation designs such as the flash translation layer protocol (FTL), NAND flash translation layer protocol (NFTL), and block-level flash translation layer protocol (BL). A w... View full abstract»

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  • Model-Driven System Capacity Planning under Workload Burstiness

    Publication Year: 2010, Page(s):66 - 80
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2102 KB) | HTML iconHTML

    In this paper, we define and study a new class of capacity planning models called MAP queueing networks. MAP queueing networks provide the first analytical methodology to describe and predict accurately the performance of complex systems operating under bursty workloads, such as multitier architectures or storage arrays. Burstiness is a feature that significantly degrades system performance and th... View full abstract»

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  • Conversion Algorithms and Implementations for Koblitz Curve Cryptography

    Publication Year: 2010, Page(s):81 - 92
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2251 KB) | HTML iconHTML

    In this paper, we discuss conversions between integers and tau-adic expansions and we provide efficient algorithms and hardware architectures for these conversions. The results have significance in elliptic curve cryptography using Koblitz curves, a family of elliptic curves offering faster computation than general elliptic curves. However, in order to enable these faster computations, scalars nee... View full abstract»

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  • Independent Spanning Trees on Multidimensional Torus Networks

    Publication Year: 2010, Page(s):93 - 102
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1195 KB) | HTML iconHTML

    Two spanning trees rooted at vertex r in a graph G are called independent spanning trees (ISTs) if for each vertex v in G, vner, the paths from vertex v to vertex r in these two trees are internally distinct. If the connectivity of G is k, the IST problem is to construct k ISTs rooted at each vertex. The IST problem has found applications in fault-tolerant broadcasting, but it is still open for ge... View full abstract»

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  • Scalable Node-Level Computation Kernels for Parallel Exact Inference

    Publication Year: 2010, Page(s):103 - 115
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2451 KB) | HTML iconHTML

    In this paper, we investigate data parallelism in exact inference with respect to arbitrary junction trees. Exact inference is a key problem in exploring probabilistic graphical models, where the computation complexity increases dramatically with clique width and the number of states of random variables. We study potential table representation and scalable algorithms for node-level primitives. Bas... View full abstract»

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  • Integrating Evolutionary Computation with Abstraction Refinement for Model Checking

    Publication Year: 2010, Page(s):116 - 126
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2276 KB) | HTML iconHTML

    Model checking for large-scale systems is extremely difficult due to the state explosion problem. Creating useful abstractions for model checking task is a challenging problem, often involving many iterations of refinement. In this paper we consider techniques for model checking in the counter example-guided abstraction refinement. The state separation problem is one popular approach in counterexa... View full abstract»

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  • Predictive Temperature-Aware DVFS

    Publication Year: 2010, Page(s):127 - 133
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1676 KB) | HTML iconHTML

    In this paper, we propose predictive temperature-aware dynamic voltage and frequency scaling (DVFS) using the performance counters that are already embedded in commercial microprocessors. By using the performance counters and simple regression analysis, we can predict the localized temperature and efficiently scale the voltage/frequency. When localized thermal problems that were not detected by th... View full abstract»

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  • Proofs of Correctness and Properties of Integer Adder Circuits

    Publication Year: 2010, Page(s):134 - 136
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (79 KB) | HTML iconHTML

    Adder circuits have been extensively studied. Their formal properties are well known, but the proofs are either incomplete or difficult to find. This short contribution intends to integrate all formal proofs related to adders in a single place and to add the details when necessary. The presentation is accessible to general VLSI designer. Another goal of this study is to put together relevant mater... View full abstract»

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  • Comment on "Performability Analysis: A New Algorithm

    Publication Year: 2010, Page(s):137 - 138
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (294 KB) | HTML iconHTML

    The paper "performability analysis: a new algorithmrdquo describes an algorithm for computing the complementary distribution of the accumulated reward over an interval of time in a homogeneous Markov process. In this comment, we show that in two particular cases, one of which is quite frequent, small modifications of the algorithm may reduce significantly its storage complexity. View full abstract»

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  • 2009 Reviewers List

    Publication Year: 2010, Page(s):139 - 143
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  • Call for Papers: Special Section on Dependable Computer Architecture

    Publication Year: 2010, Page(s): 144
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  • TC Information for authors

    Publication Year: 2010, Page(s): c3
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  • [Back cover]

    Publication Year: 2010, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org