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IEEE Design & Test of Computers

Issue 6 • Nov.-Dec. 2009

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Displaying Results 1 - 24 of 24
  • [Front cover]

    Publication Year: 2009, Page(s): c1
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  • Front Covers 
  • Table of Contents

    Publication Year: 2009, Page(s): c2
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  • Toc 
  • Departments [Table of Contents]

    Publication Year: 2009, Page(s): 1
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  • Design for reliability and robustness

    Publication Year: 2009, Page(s):2 - 3
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  • Call for Papers

    Publication Year: 2009, Page(s): 4
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  • Masthead

    Publication Year: 2009, Page(s): 5
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  • Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design

    Publication Year: 2009, Page(s):6 - 7
    Cited by:  Papers (9)
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  • Reliability Implications of Bias-Temperature Instability in Digital ICs

    Publication Year: 2009, Page(s):8 - 17
    Cited by:  Papers (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1225 KB) | HTML iconHTML

    Bias temperature instability (BTI) is one of the major reliability challenges in nanoscale CMOS technology. This article investigates the severity of such degradation in logic and memory circuits. The simulation results reveal that BTI poses severe constraints on reliable memory design, especially in the presence of random process variations. View full abstract»

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  • Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements

    Publication Year: 2009, Page(s):18 - 27
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3467 KB) | HTML iconHTML

    Low-k dielectric breakdown and stress migration have emerged as new sources of wearout for on-chip interconnect. This article analyzes statistical data from a 45-nm test chip and constructs a methodology to determine the lifetime of low-k materials under process variations. View full abstract»

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  • Overcoming Early-Life Failure and Aging for Robust Systems

    Publication Year: 2009, Page(s):28 - 39
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB) | HTML iconHTML

    The prospect of system failure has increased because of device and chip-level effects in the late CMOS era. In this article, the authors present novel system-level architecture and design innovations to cope with these lifetime reliability challenges. At nanometer-scale geometries, several hardware failure mechanisms, which were largely benign in the past, are becoming visible at the system level.... View full abstract»

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  • Sensor-Driven Reliability and Wearout Management

    Publication Year: 2009, Page(s):40 - 49
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2869 KB) | HTML iconHTML

    In this article, we propose two new approaches to improve existing DRM (dynamic reliability management) methodology First, we propose reliability sensors that use small replicated circuits to directly measure device wearout on the chip. A direct degradation measurement by these sensors removes a layer of uncertainty introduced because of inaccurate calibration of the degradation models. Note that,... View full abstract»

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  • A Novel Simulation Fault Injection Method for Dependability Analysis

    Publication Year: 2009, Page(s):50 - 61
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2098 KB) | HTML iconHTML

    Presilicon testing and verification is a crucial step in qualifying the RTL for the subsequent implementation phases. This article presents a novel simulation-based fault injection methodology that is applied at the system description level, as opposed to the lower, flattened RT level, in order to reduce simulation time. View full abstract»

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  • Reliability Challenges and System Performance at the Architecture Level

    Publication Year: 2009, Page(s):62 - 73
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2877 KB) | HTML iconHTML

    The challenge for future reliable systems is to provide protection against all types of errors while delivering performance and managing power and complexity. This article gives an overview of reliability challenges, and describes techniques and methodologies that can be used to achieve error detection and correction in a complex, high-performance system. View full abstract»

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  • EOC: Electronic Building Blocks for Embedded Systems

    Publication Year: 2009, Page(s):74 - 83
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5097 KB) | HTML iconHTML

    The embedded-object concept, EOC, applies common object-oriented software methods to Lego-like hardware-software entities. These modular entities, representing objects in object-oriented design, function as electronic building blocks that can be assembled into new embedded systems. The goal of the EOC is to make embedded-system design faster and easier while preserving the commercial applicability... View full abstract»

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  • Accelerating Emulation and Providing Full Chip Observability and Controllability

    Publication Year: 2009, Page(s):84 - 94
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (202 KB) | HTML iconHTML

    The authors deploy an emulation framework that automatically transforms certain hardware description language (HDL) parts of the testbench into synthesizable code to offload the software simulator and minimize the communication overhead. They also extend this architecture by adding multiple fast scan chain paths in the design to provide full circuit observability and controllability on the fly. View full abstract»

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  • Conference Reports

    Publication Year: 2009, Page(s): 95
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (107 KB) | HTML iconHTML Multimedia Media

    Design and Test Conference Reports View full abstract»

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  • Test Technology TC Newsletter

    Publication Year: 2009, Page(s): 96
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  • Book Reviews: A guide for the wrapper perplexed [a review of The Core Test Wrapper Handbook by da Silva et al.; 2006)]

    Publication Year: 2009, Page(s):98 - 99
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  • CEDA Currents

    Publication Year: 2009, Page(s):100 - 101
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  • Design Automation Technical Committee Newsletter

    Publication Year: 2009, Page(s):102 - 103
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  • The Last Byte: Too many reboots

    Publication Year: 2009, Page(s): 104
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (74 KB) | HTML iconHTML

    Rebooting, long the required method to get a failed computer or computerized device up and running again, is still the procedure of choice for some complicated yet otherwise deceptively ordinary devices today. View full abstract»

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  • [Back cover - Advertisement]

    Publication Year: 2009, Page(s): c3
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  • [Back cover - Advertisement]

    Publication Year: 2009, Page(s): c4
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  • Annual Index

    Publication Year: 2009, Page(s): 0
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty