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Embedded Systems Letters, IEEE

Issue 2 • Date Aug. 2009

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Displaying Results 1 - 14 of 14
  • Table of contents

    Page(s): C1
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  • IEEE Embedded Systems Letters publication information

    Page(s): C2
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  • Temperature Compensated Time Synchronization

    Page(s): 37 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (458 KB) |  | HTML iconHTML  

    Time synchronization in embedded sensor networks is an important service for correlating data between nodes and communication scheduling. While many different approaches to the problem are possible, one major effect of clock frequency difference between nodes, environmental temperature changes, has often been left out of the solution. The common assumption that the temperature is static over a certain period of time is often used as an excuse to assume constant frequency errors in a clock. This assumption forces synchronization protocols to resynchronize too often. While there exists hardware solutions to this problem, their prohibitive high cost and power consumption make them unsuitable for some applications, such as wireless sensor networks. Temperature compensated time synchronization (TCTS) exploits the on-board temperature sensor existing in many sensor network platforms. It uses this temperature sensor to autonomously calibrate the local oscillator and removes effects of environmental temperature changes. This allows a time synchronization protocol to increase its resynchronization period, without loosing synchronization accuracy, and thus saves energy and communication overhead. In addition, TCTS provides a stable clock source when radio communication is impaired. We present the theory behind TCTS, and provide initial results of a simulated comparison of TCTS and the flooding time synchronization protocol. View full abstract»

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  • Embedded Software Design of Scalable Low-Area Elliptic-Curve Cryptography

    Page(s): 42 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (361 KB) |  | HTML iconHTML  

    In this letter, a fully software implementation of scalable elliptic curve cryptography (ECC) over GF(2m) on a tiny microcontroller (PicoBlaze) is presented. The implementation performs the whole ECC point multiplication in only 0.257 s for m =113 bit , 0.405 s for m = 131 bit , 0.75 s for m = 163 bit and in 1.23 s for m = 193 bit . This design, either standalone or as part of a software-hardware codesign, opens up the potential of scalable public key cryptography to be used in secure resource constrained applications. View full abstract»

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  • SCoPE: Towards a Systolic Array for SVM Object Detection

    Page(s): 46 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (617 KB) |  | HTML iconHTML  

    This paper presents SCoPE (systolic chain of processing elements), a first step towards the realization of a generic systolic array for support vector machine (SVM) object classification in embedded image and video applications. SCoPE provides efficient memory management, reduced complexity, and efficient data transfer mechanisms. The proposed architecture is generic and scalable, as the size of the chain, and the kernel module can be changed in a plug and play approach without affecting the overall system architecture. These advantages provide versatility, scalability and reduced complexity that make it ideal for embedded applications. Furthermore, the SCoPE architecture is intended to be used as a building block towards larger systolic systems for multi-input or multi-class classification. Simulation results indicate real-time performance, achieving face detection at ~33 frames per second on an FPGA prototype. View full abstract»

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  • A Layer-Multiplexed 3D On-Chip Network Architecture

    Page(s): 50 - 55
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (274 KB) |  | HTML iconHTML  

    Programmable many-core processors are poised to become a major design option for many embedded applications. In the design of power-efficient embedded many-core processors, the architecture of the on-chip network plays a central role. Many designs have relied on a 2D mesh architecture as the underlying communication fabric. With the emergence of 3D technology, new on-chip network architectures are possible. In this paper, we propose a novel layer-multiplexed (LM) 3D network architecture that takes advantage of the short interlayer wiring delays enabled in 3D technology. In particular, the LM architecture replaces the one-layer-per-hop routing in a conventional 3D mesh with simpler vertical demultiplexing and multiplexing structures. When combined with a layer load-balanced oblivious routing algorithm, it can achieve the same worst-case throughput as the best known oblivious routing algorithm on a conventional 3D mesh. However, in comparison to a conventional 3D mesh, the LM architecture consumes 27% less power, attains 14.5% higher average throughput, and achieves 33% lower worst-case hop count on a 4 times 4 times 4 topology. View full abstract»

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  • BOUNCE: A New High-Resolution Time-Interval Measurement Architecture

    Page(s): 56 - 59
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB) |  | HTML iconHTML  

    Measuring the duration of a time interval is a discretization process in which an input signal is sampled at discrete time steps. Most digital systems generate these time steps by active components, such as a generator, flip-flops, dedicated delay elements, gates, inverters, and the like, whose signal propagation time determine the system's resolution. This paper presents a new time-interval measurement architecture, called BOUNCE, in which the delays are realized by the simplest elements possible: the (metal) wires between the logic elements within the chip. Standard RS latches serve as the sampling units. Even though the requirements with respect to setup and hold times of these latches are not met, the architecture operates quite reliably: on an Altera Stratix II field-programmable gate array, BOUNCE yields a time resolution better than 4 ps. Due to its architecture, BOUNCE is ideally suited to be implemented on field-programmable gate arrays and can thus be realized as an embedded system on its own or as part of an existing one. View full abstract»

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  • IEEE Embedded Systems Letters

    Page(s): 60
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  • The Cyber-Physical Systems Week 2010 (CPSWEEK 2010)

    Page(s): 61
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    Page(s): 62
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    Page(s): 63
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    Page(s): 64
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  • IEEE Embedded Systems Letters Information for authors

    Page(s): C3
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  • Blank page [back cover]

    Page(s): C4
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Aims & Scope

The IEEE EMBEDDED SYSTEMS LETTERS (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software.

Full Aims & Scope

Meet Our Editors

EDITOR-IN-CHIEF
Krithi Ramamritham
Department of Computer Science and Engineering
Indian Institute of Technology Bombay

DEPUTY EDITOR-IN-CHIEF
Catherine Gebotys
Department of Electrical and Computer Engineering
University of Waterloo