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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 11 • Date Nov. 2009

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Displaying Results 1 - 20 of 20
  • Table of contents

    Publication Year: 2009 , Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2009 , Page(s): C2
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  • A 0.5-V Wideband Amplifier for a 1-MHz CT Complex Delta-Sigma Modulator

    Publication Year: 2009 , Page(s): 805 - 809
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (358 KB) |  | HTML iconHTML  

    This brief presents a fully differential wideband amplifier for 0.5-V supply. The amplifier employs a gate-input two-stage topology and a DC common-mode feedback circuit with a Miller-amplified capacitor for frequency compensation. Designed in a 130-nm triple-well complementary metal-oxide-semiconductor process with regular VT transistors, the amplifier achieves a simulated performance of 51-dB DC open-loop gain, 112-MHz unity gain bandwidth, and 67deg phase margin with a load of 6.5 pF/19.6 kOmega , and consumes 600 muW at 0.5-V supply. The proposed amplifier is incorporated in a continuous-time complex delta-sigma modulator with a 1-MHz signal bandwidth and 64times oversampling ratio. In the simulations, the modulator achieves a 72.5-dB signal-to-noise-plus-distortion ratio and consumes 2.3 mW at 0.5 V. View full abstract»

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  • A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V

    Publication Year: 2009 , Page(s): 810 - 814
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (755 KB) |  | HTML iconHTML  

    A comparator in a low-power 65-nm complementary metal-oxide-semiconductor process (only standard transistors with threshold voltage Vt ap 0.4 V were used) is presented, where the circuit of a conventional latch-type comparator consisting of two cross-coupled inverters is modified for fast operation, even with 0.6 GHz at a low supply voltage of 0.65 V. The advantages of a high-impedance input, rail-to-rail output swing, robustness against the influence of mismatch, and no static power consumption are kept. To achieve a bit error rate of 10-9 at 1.2-V supply, an amplitude at the input of 16.5 mV at 4 GHz has to be applied. If the supply voltage is lowered, 12.1 mV at 0.6 GHz/0.65 V is necessary. The power consumption of the comparator is 2.88 mW at 5 GHz (1.2 V) and 128 muW at 0.6 GHz (0.65 V). Simulations show an offset standard deviation of about 6.1 mV at 0.65-V supply. With an on-chip measurement circuit, the delay time of the comparator of, e.g., 104 ps for 15-mV input amplitude at 1.2-V supply, is obtained. View full abstract»

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  • Digital Peak Current Control for Switching DC–DC Converters With Asymmetrical Dual-Edge Modulation

    Publication Year: 2009 , Page(s): 815 - 819
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (487 KB) |  | HTML iconHTML  

    An asymmetrical dual-edge modulation (ADM) method applied to digital peak current (DPC)-controlled switching dc-dc converters is proposed in this brief. Steady-state and transient performance comparison of DPC-controlled buck converters with ADM and conventional symmetrical dual-edge modulation (SDM) is presented and verified by experimental results. Comparison studies show that the steady-state and transient performances of DPC with ADM are better than those of DPC with SDM. View full abstract»

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  • Adaptive Time-Interleaved ADC Offset Compensation by Nonwhite Data Chopping

    Publication Year: 2009 , Page(s): 820 - 824
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (573 KB) |  | HTML iconHTML  

    This brief makes an important step forward on the ideas first presented in our earlier paper about the use of nonwhite chopping sequences for offset compensation in time-interleaved analog-to-digital converters. More specifically, we present an adaptive system that takes advantage of nonwhite chopping in slowly nonstationary settings. Simulations show that by using this technique the estimation time and the signal-to-noise ratio are significantly improved with respect to white chopping. View full abstract»

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  • A 0.6-V Delta–Sigma Modulator With Subthreshold-Leakage Suppression Switches

    Publication Year: 2009 , Page(s): 825 - 829
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (319 KB) |  | HTML iconHTML  

    A 0.6-V 34-muW delta-sigma modulator implemented by using a standard 0.13-mum complementary metal-oxide-semiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order delta-sigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 muW for the modulator, and the core chip size is 0.33 mm2 . View full abstract»

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  • Design and Optimization of a Class-E Amplifier for a Loosely Coupled Planar Wireless Power System

    Publication Year: 2009 , Page(s): 830 - 834
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    In wireless power systems for charging battery-operated devices, the selection of component values guaranteeing certain desired performance characteristics can be a tedious trial-and-error process, either sweeping component values in circuit simulations or changing components by hand. This difficulty is compounded by the variable nature of the load resistance presented by a device under charge. This brief considers component selection for a specific wireless power system architecture, which is an open-loop class-e inverter using a series-parallel arrangement for load impedance transformation. Formulas for the optimal receiver, transmitter, and class-e components are derived given a set of constraints on the resistance, phase, quality factor, and drain voltage waveform. Using a 16 cm times 18 cm primary and a 4 cm times 5 cm secondary coil, the derived formulas are used to build a wireless power system. We show that the system has desirable performance characteristics, including a power delivery of over 3.7 W, peak efficiency of over 66%, and decreasing power delivery with increasing load resistance. View full abstract»

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  • Noise Analysis and Minimization in Bang-Bang Digital PLLs

    Publication Year: 2009 , Page(s): 835 - 839
    Cited by:  Papers (22)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    In digital bang-bang phase-locked loops (BBPLLs), both the hard nonlinearity of the phase detector and the frequency granularity of the digitally controlled oscillator (DCO) can give rise to undesired tones or peaking in the output spectrum. This work derives the maximum ratio between DCO resolution and jitter, which avoids limit cycles, in the case of dominant DCO noise over reference noise. Moreover, the output jitter is expressed in closed form as a function of the loop parameters and latency, revealing the existence of a minimum and suggesting an optimum design criterion. Finally, an estimation of the BBPLL output spectrum taking into account the quantization noise is provided. View full abstract»

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  • Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities

    Publication Year: 2009 , Page(s): 840 - 844
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (369 KB) |  | HTML iconHTML  

    To alleviate the image-rejection requirements of the front-end filters and the feedback digital-to-analog converter (DAC) matching requirements, an oversampling complex discrete-time (DT) DeltaSigma analog-to-digital converter (ADC) with a signal-transfer function that achieves significant filtering of interfering signals is proposed. With a filtering signal transfer function (STF) and stopband attenuation greater than 30 dB, the DeltaSigma modulator reduces the intermodulation of the desired signal and the interfering signals at the input of a quantizer, and also avoids feedback of high-frequency interfering signals at the input of the modulator. This filtering of the interfering signals reduces sensitivity to DAC nonlinearities. The reported DT complex DeltaSigma ADC is intended for digital television (DTV) receiver applications. With a maximum intended sampling frequency of 128 MHz and an oversampling ratio of 16, the ADC has been designed to support a maximum DTV signal bandwidth of 8 MHz. The IC achieved a 70.9-dB signal-to-noise-and-distortion ratio over a 6-MHz band centered around 3 MHz. The image-rejection ratio of the DeltaSigma ADC was measured to be greater than 65 dB. The fabricated chip consumes 122.4 mW and occupies a silicon area of 2.15 mm2. View full abstract»

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  • Stability Analysis of Periodic Orbits of Nonautonomous Piecewise-Linear Systems by Mapping Approach

    Publication Year: 2009 , Page(s): 845 - 849
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (226 KB) |  | HTML iconHTML  

    In this brief, we present an exact stability analysis for periodic orbits of nonautonomous piecewise-linear systems. The described discrete-time maps are derived by connecting solutions at the switched points and solving relevant sets of linear differential equations. The coordinates of the switched points of the periodic orbit on each switching surface and the corresponding Jacobians are obtained. Theoretical analysis and simulation results for the piecewise-linear Duffing oscillator and Colpitts oscillator are presented to illustrate the proposed method. View full abstract»

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  • A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop

    Publication Year: 2009 , Page(s): 850 - 854
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (617 KB) |  | HTML iconHTML  

    A 20-MHz to 3-GHz wide-range multiphase delay-locked loop (DLL) has been realized in 90-nm CMOS technology. The proposed delay cell extends the operation frequency range. A scaling circuit is adopted to lower the large delay gain when the frequency of the input clock is low. The core area of this DLL is 0.005 mm2. The measured power consumption values are 0.4 and 3.6 mW for input clocks of 20 MHz and 3 GHz, respectively. The measured peak-to-peak and root-mean-square jitters are 2.3 and 16 ps at 3 GHz, respectively. View full abstract»

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  • A Split-Based Digital Background Calibration Technique in Pipelined ADCs

    Publication Year: 2009 , Page(s): 855 - 859
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    A digital background calibration technique is proposed to correct gain errors in pipelined analog-to-digital converters (ADCs). The calibration technique performs the error estimation and the adaptive error correction based on the concept of split ADCs. With the 1- or 1.5-bit realization in pipelined stages, capacitor-mismatch errors can be merged with gain errors, and the proposed calibration technique can be utilized. Behavioral simulations show that the signal-to-noise-and-distortion ratio of a 12-bit pipelined ADC with an 8-bit gain accuracy and the capacitor mismatch sigma = 0.125% can be improved from 56.4 to 73.8 dB. The calibration process converges in approximately 200 000 cycles. View full abstract»

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  • A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming

    Publication Year: 2009 , Page(s): 860 - 864
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (526 KB) |  | HTML iconHTML  

    State-of-the-art phase-domain all-digital phase-locked loops (ADPLLs) require a retimed reference clock to synchronize the digitally controlled oscillator (DCO) output frequency and the reference clock frequency. Therefore, the entire digital logic is operated with a periodically nonuniform clock. Due to on-chip coupling effects, the DCO output frequency is pulled with the edges of the retimed reference clock, producing undesired spurs in the phase noise power spectrum. In this brief, we analyze and classify the spur generation from a signal processing point of view and propose an alternative ADPLL implementation that abandons the retiming mechanism. Thus, the entire ADPLL can be clocked with a uniform reference clock, and consequently, side spurs are avoided. Behavioral simulations verify the spur analysis and emphasize the improved behavior of the proposed synchronous reference architecture. View full abstract»

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  • A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories

    Publication Year: 2009 , Page(s): 865 - 869
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (457 KB) |  | HTML iconHTML  

    An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in nor flash memories with the process shrinking beyond 45 nm. A novel fast-decoding algorithm is developed to speed up the BCH decoding process using iteration-free solutions and division-free transformations in finite fields. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of a two-cell decoder that is suitable for an MLC flash memory is proposed to obtain a good time-area tradeoff. Experimental results show that the latency of the proposed two-cell BCH decoder is only 7.5 ns, which satisfies the fast-access-time requirements of nor flash memories. View full abstract»

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  • A Fast Spline Curve Rendering Accelerator Architecture

    Publication Year: 2009 , Page(s): 870 - 874
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (574 KB) |  | HTML iconHTML  

    Spline curve rendering is an essential operation in modern 2-D graphic applications. Different from the software acceleration approach by graphic processor units, this brief presents a very large scale integration hardware accelerator architecture for supporting fast curve rendering. Many existing accelerators employ a sequential forward-difference algorithm, where a step size is used in calculating the next sample on the curve. The problem of hardware-based curve rendering is that feedback loops are required to accumulate the difference, and these loops inhibit many traditional performance-enhancement strategies such as unfolding and pipelining. This brief proposes a different parallel design approach by transforming the difference equation set into parallel ones. Each equation has to be equipped with the same increased step size but accumulated starting from different initial values. Although more initial values must be precomputed, this computation can itself be sped up by using the accelerator. The proposed design can be applied not only to cubic spline curves but also to any curves defined by parameterized polynomial functions. View full abstract»

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  • Conditional Diagnosability of Matching Composition Networks Under the PMC Model

    Publication Year: 2009 , Page(s): 875 - 879
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (130 KB) |  | HTML iconHTML  

    In the work of Lai in 2005, they proposed a new measure for fault diagnosis of systems, namely, conditional diagnosability. It assumes that no fault set can contain all the neighbors of any vertex in the system. In the same paper, they showed that the conditional diagnosability of hypercube Qn is 4(n - 2) + 1 for n ges 5. In this brief, we generalize this result by considering a family of more popular networks, namely, matching composition networks (MCNs), which are a class of networks composed of two components of the same order linked by a perfect matching under PMC (Preparata, Metze and Chien) model. We determine in Theorem 7 the conditional diagnosability for some MCNs, from which we deduce that the hypercube Qn, the crossed cube CQn, the twisted cube TQn, and the MOumlbius cube MQn all have the same conditional diagnosability of 4(n - 2) + 1 for n ges 5. We show that the bijective connection (BC) networks in the work of Fan and He in 2003 and the work of Zhu in 2008 satisfy the conditions of Theorem 7, and thus, our conditional diagnosability result also applies to BC networks. Finally, we show that the MCNs satisfying the conditions of Theorem 7 are more general than the BC networks. View full abstract»

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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Publication Year: 2009 , Page(s): 880
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    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2009 , Page(s): C3
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    Freely Available from IEEE
  • Blank page [back cover]

    Publication Year: 2009 , Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope