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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 12 • Dec. 2009

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2009, Page(s):C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2009, Page(s): C2
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  • Editorial

    Publication Year: 2009, Page(s): 1785
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  • Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008

    Publication Year: 2009, Page(s):1786 - 1787
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  • Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions

    Publication Year: 2009, Page(s):1788 - 1801
    Cited by:  Papers (21)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1608 KB) | HTML iconHTML

    Customized processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must take into account; die area and energy efficiency are equally important. Resource sharing during synthesis of instruction set extensions (ISEs) can significantly reduce the die area and energy consumption of a customized processor. T... View full abstract»

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  • TRaX: A Multicore Hardware Architecture for Real-Time Ray Tracing

    Publication Year: 2009, Page(s):1802 - 1815
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (819 KB) | HTML iconHTML

    Threaded Ray eXecution (TRaX) is a highly parallel multithreaded multicore processor architecture designed for real-time ray tracing. The TRaX architecture consists of a set of thread processors that include commonly used functional units (FUs) for each thread and that share larger FUs through a programmable interconnect. The memory system takes advantage of the application's read-only access to t... View full abstract»

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  • ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration

    Publication Year: 2009, Page(s):1816 - 1829
    Cited by:  Papers (29)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB) | HTML iconHTML

    Application-specific multiprocessor systems-on-chip (MPSoCs) are usually designed by using a platform-based approach, where a wide range of customizable parameters can be tuned to find the best tradeoff in terms of the selected figures of merit (such as energy, delay, and area). This optimization phase is called design space exploration (DSE), and it usually consists of a ... View full abstract»

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  • Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies

    Publication Year: 2009, Page(s):1830 - 1843
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2382 KB) | HTML iconHTML

    Wireless Internet-access technologies have significant market potential, particularly the Worldwide Interoperability for Microwave Access (WiMAX) protocol which can offer data rates of tens of megabits per second. A significant demand for embedded high-performance WiMAX solutions is forcing designers to seek single-chip multicore systems that offer competitive advantages in terms of all performanc... View full abstract»

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  • High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier

    Publication Year: 2009, Page(s):1844 - 1856
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (884 KB) | HTML iconHTML

    Multiplying a signal by a known constant is an essential operation in digital signal processing algorithms. In many application scenarios, an input or output signal is repeatedly multiplied by several predefined constants at different instances. These temporal redundancies can be exploited for the design of an efficient reconfigurable constant multiplier (RCM). An RCM achieves greater hardware sav... View full abstract»

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  • ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration

    Publication Year: 2009, Page(s):1857 - 1869
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (893 KB) | HTML iconHTML

    This paper presents reflective simulation platform (ReSP), a transaction-level multiprocessor simulation platform based on the integration of SystemC and Python. ReSP exploits the concept of reflection, enabling the integration of SystemC components without source-code modifications and providing full observability of their internal state. ReSP offers fine-grained simulation control and supports t... View full abstract»

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  • Thermal Balancing Policy for Multiprocessor Stream Computing Platforms

    Publication Year: 2009, Page(s):1870 - 1882
    Cited by:  Papers (29)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (956 KB) | HTML iconHTML

    Die-temperature control to avoid hotspots is increasingly critical in multiprocessor systems-on-chip (MPSoCs) for stream computing. In this context, thermal balancing policies based on task migration are a promising approach to redistribute power dissipation and even out temperature gradients. Since stream computing applications require strict quality of service and timing constraints, the real-ti... View full abstract»

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  • Threshold Testing: Improving Yield for Nanoscale VLSI

    Publication Year: 2009, Page(s):1883 - 1895
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (729 KB) | HTML iconHTML

    Yields for digital very-large-scale-integration chips have been declining in the recent years, and the decline is accelerating as the technology moves deep into nanoscale. Recently, we have proposed the notion of error tolerance to improve yields for a wide range of high-performance digital applications, including audio, speech, video, graphics, visualization, games, and wireless communication. Er... View full abstract»

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  • Corrections to “Quadratic Backward Propagation of Variance for Nonlinear Statistical Circuit Modeling” [Sep 09 1428-1432]

    Publication Year: 2009, Page(s): 1896
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (49 KB) | HTML iconHTML

    In the above titled paper (ibid., vol. 28, no. 9, pp. 1428-1432, Sep. 09), there was a typo in (1), and (10) and (11) were incorrect of there is more than one forward propagation of variance (FPV) variable. The correct expressions for these three equations are presented here. View full abstract»

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  • ISCAS 2010 nono-bio circuit fabrics and systems

    Publication Year: 2009, Page(s): 1897
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2009, Page(s): 1898
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  • 2009 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 28

    Publication Year: 2009, Page(s):1899 - 1917
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  • Why we joined ... [advertisement]

    Publication Year: 2009, Page(s): 1918
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  • IEEE 2009 Membership Application

    Publication Year: 2009, Page(s):1919 - 1920
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2009, Page(s): C3
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu