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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 11 • Date Nov. 2009

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Displaying Results 1 - 18 of 18
  • Table of contents

    Publication Year: 2009 , Page(s): C1
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2009 , Page(s): C2
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  • Analysis and Design of the 0.13- \mu\hbox {m} CMOS Shunt–Series Series–Shunt Dual-Feedback Amplifier

    Publication Year: 2009 , Page(s): 2373 - 2383
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1192 KB) |  | HTML iconHTML  

    This paper demonstrates the design methodology of the shunt-series series-shunt dual-feedback Meyer wideband amplifier. The small-signal S-parameters are obtained for the first time using the pole-and-zero analysis, thus giving the RF designers a detailed insight into the Meyer amplifier. A 10-GHz wideband amplifier is demonstrated in this paper, using 0.13-mum CMOS technology to verify our design theory. The experimental results of the S-parameters highly agree with our theory. View full abstract»

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  • A Pixel-Parallel Self-Similitude Processing for Multiple-Resolution Edge-Filtering Analog Image Sensors

    Publication Year: 2009 , Page(s): 2384 - 2392
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2235 KB) |  | HTML iconHTML  

    A pixel-parallel self-similitude computation architecture has been developed for multiple-resolution directional edge filtering based on focal-plane image processing. The self-similitude organization has enabled pixel-by-pixel multiple-resolution image filtering with minimal complexity in interconnects. As a result, it has become possible to accomplish any (1/2)n-resolution directional edge filtering in (n+2) steps. An analog edge-filtering chip implemented using a switched floating-gate MOS (neuMOS) technology that is capable of performing four-directional edge filtering at full, half, and quarter resolutions was designed and fabricated in a 0.35-mum 3-metal CMOS technology. The concept has been experimentally verified using the fabricated chip, and the four-directional edge filtering at full, half, and quarter resolutions was demonstrated by measurement. View full abstract»

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  • A Spike-Latency Model for Sonar-Based Navigation in Obstacle Fields

    Publication Year: 2009 , Page(s): 2393 - 2401
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (967 KB) |  | HTML iconHTML  

    The rapid control of sonar-guided vehicles through obstacle fields has been a goal of robotics for decades. How sensory data are represented strongly affects how obstacles and goal information can be combined to select a direction of travel. Many approaches combine attractive and repulsive effects to steer; we have implemented an algorithm that first evaluates the desirability of different directions followed by a winner-take-all (WTA) mechanism to guide steering. We describe a neuromorphic VLSI implementation of this algorithm using the inherent echo delay of obstacles to produce a range-dependent gain in a ldquorace-to-first-spikerdquo neural WTA circuit. View full abstract»

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  • Analog Decoder Performance Degradation Due to BJTs' Parasitic Elements

    Publication Year: 2009 , Page(s): 2402 - 2410
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (705 KB) |  | HTML iconHTML  

    This paper presents the effect of bipolar junction transistors' (BJTs) parasitic elements on the decoding performance of a BiCMOS analog decoder. The transistors' parasitic effects are taken into account to develop a more accurate behavioral model of the computing nodes. The model is applied to double-binary 0.25-mum BiCMOS analog decoders. Behavioral simulations show that the BJTs' parasitic elements deteriorate the error-correcting performance of a stand-alone a posteriori probability (APP) decoder by 0.5 dB compared with the ideal bit error rate (BER). In a turbo scheme, the loss is reduced to 0.2 dB for a BER that is smaller than 10-2. A simple solution based on an nMOS amplifier is proposed to counterbalance the dominant parasitic element. The amplifier reduces the degradation by 0.2 dB for the APP decoder. However, the turbo decoder is improved only for a BER above 10-2. View full abstract»

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  • Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits

    Publication Year: 2009 , Page(s): 2411 - 2424
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2733 KB) |  | HTML iconHTML  

    As the size of CMOS devices is scaled down to nanometers, noise can significantly affect circuit performance. Because noise is random and dynamic in nature, a probabilistic-based approach is better suited to handle these types of errors compared with conventional CMOS designs. In this paper, we propose a cost-effective probabilistic-based noise-tolerant circuit-design methodology. Our cost-effective method is based on master-and-slave Markov random field (MRF) mapping and master-and-slave MRF logic-gate construction. The resulting probabilistic-based MRF circuit trades hardware cost for circuit reliability. To demonstrate a noise-tolerant performance, an 8-bit MRF carry-lookahead adder (MRF_CLA) was implemented using the 0.13-mum CMOS process technology. The chip measurement results show that the proposed master-and-slave MRF_CLA can provide a 7.00 times 10-5 bit-error rate (BER) under 10.6-dB signal-to-noise ratio, while the conventional CMOS_CLA can only provide 8.84 times 10-3 BER. Because of high noise immunity, the master-and-slave MRF_CLA can operate under 0.25 V to tolerate noise interference with only 1.9 muW/MHz of energy consumption. Moreover, the transistor count can be reduced by 42% as compared with the direct-mapping MRF_CLA design . View full abstract»

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  • Architecture and FPGA Design of Dichotomous Coordinate Descent Algorithms

    Publication Year: 2009 , Page(s): 2425 - 2438
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (733 KB) |  | HTML iconHTML  

    In the areas of signal processing and communications, such as antenna-array beamforming, adaptive filtering, multiuser and multiple-input-multiple-output (MIMO) detection, channel estimation and equalization, echo and interference cancellation, and others, solving linear systems of equations often provides an optimal performance. However, this is also a very complicated operation that designers try to avoid by proposing different suboptimal techniques. The dichotomous coordinate descent (DCD) algorithm allows linear systems of equations to be solved with high computational efficiency. In this paper, we present architectures and field-programmable gate-array (FPGA) designs of two variants of the DCD algorithm, which are known as cyclic and leading DCD algorithms. For each of these techniques, we present serial designs, group-2 and group-4 designs, as well as a design with parallel update of the residual vector for the cyclic DCD algorithm. These designs have different degrees of parallelism, thus enabling a tradeoff between FPGA resources and computation time. The serial designs require the smallest FPGA resources; they are well suited for applications where many parallel solvers are required, e.g., for detection in MIMO-orthogonal-frequency-division-multiplexing communication systems. The parallelism introduced in the proposed group-2 and group-4 designs allows faster convergence to the true solution at the expense of an increase in FPGA resources. The design with parallel update of the residual vector provides the fastest convergence speed; however, if the system size is high, it may result in a significant increase in FPGA resources. The proposed fixed-point designs provide an accuracy performance that is very close to the performance of floating-point counterparts and require significantly lower FPGA resources than techniques based on QR decomposition. View full abstract»

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  • A Fast and Power–Area-Efficient Accumulator for Flying-Adder Frequency Synthesizer

    Publication Year: 2009 , Page(s): 2439 - 2448
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1898 KB) |  | HTML iconHTML  

    The flying-adder frequency synthesis architecture is a novel approach of generating frequencies on chip. Since its invention, it has been used in many commercial products to cope with difficult frequency generation challenges. Along the course of this architecture's evolution, various circuit- and system-level problems have been resolved. In this paper, one remaining problem related to circuit implementation, namely, the construction of the accumulator, is studied. A new scheme is proposed to achieve the flying-adder accumulation function that not only has speed advantage but also is power and area efficient. The issue related to time-average frequency and jitter is also discussed. View full abstract»

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  • A Low-Complexity High-Radix RNS Multiplier

    Publication Year: 2009 , Page(s): 2449 - 2462
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (899 KB) |  | HTML iconHTML  

    A graph-based technique is introduced for the design of a class of residue arithmetic multipliers, as well as a family of new high-radix digit adders. A proposed design technique derives simple high-radix modulo-r n multipliers by optimally selecting among the variety of introduced digit adders the ones that compose a minimal-area multiplier. The proposed technique minimizes multiplier complexity by selecting digit adders that observe the constraints imposed on the maximum values of the various intermediate digits. The proposed technique leads to significant area and time improvements over previously published architectures for practical modulus cases. View full abstract»

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  • A Flexible and Scalable Structure to Compensate Frequency Response Mismatches in Time-Interleaved ADCs

    Publication Year: 2009 , Page(s): 2463 - 2475
    Cited by:  Papers (20)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (522 KB) |  | HTML iconHTML  

    In this paper, we present a flexible and scalable structure to compensate frequency response mismatches in time-interleaved analog-to-digital converters (TI-ADCs). The flexibility of the structure allows for designing compensation filters independent of the number of channels that can achieve any desired signal-to-noise ratio due to the scalability of the structure. Therefore, the compensation structure may be used to compensate time-varying frequency response mismatches in TI-ADCs, as well as to reconstruct uniform samples from nonuniformly sampled signals. We analyze the compensation structure, investigate its performance, and demonstrate application areas of the structure through numerous examples. View full abstract»

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  • Linear LMS Compensation for Timing Mismatch in Time-Interleaved ADCs

    Publication Year: 2009 , Page(s): 2476 - 2486
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    The time-interleaved architecture permits the implementation of high-frequency analog-to-digital converters (ADCs) by multiplexing the output of several time-shifted low-frequency ADCs. An issue in the design of a time-interleaved ADC is the compensation of timing mismatch, which is the difference between the ideal and real sampling instants. In this paper, we propose a compensation method that, as opposite to existing approaches, does not assume that the input signal is band limited but assumes instead that it has a stationary known power spectrum. The compensation is then designed in a statistically optimal sense. This largely reduces the compensation order required to achieve a given reconstruction accuracy. Also, under the band-limited assumption, the proposed method achieves perfect reconstruction if no constraints are imposed on the order of the compensation. Simulation results show that a rough estimate of the input spectrum can be used without much performance loss, showing that an accurate knowledge of the input spectrum is not necessarily required. View full abstract»

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  • All Digital-Quadrature-Modulator Based Wideband Wireless Transmitters

    Publication Year: 2009 , Page(s): 2487 - 2497
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1700 KB) |  | HTML iconHTML  

    A novel architecture for a fully digital wideband wireless transmitter is presented. The proposed structure replaces high-dynamic-range analog circuits with high-speed digital circuits and offers a simple and flexible architecture, which requires less area, consumes less power, and delivers higher performance compared to those of the conventional modulators used for wideband systems. The design is based on a standard 65-nm CMOS process and is suitable for integration with a digital signal processor, memory, and logic implemented in such a process. The presented transmitter is based on a novel digital quadrature modulator (DQM), which achieves digital modulation in a Cartesian coordinate system. The novel architecture employs a single converter, referred to as the differential-like digital-to-RF converter (DDRC), as it is based on fully digitally combining the quadrature baseband signals. A DDRC, which is the heart of a DQM, combines functionalities of a mixer, a digital-to-analog converter, and an RF filter into a single circuit. The total area for the digital blocks is 0.04 mm2, with a power consumption of roughly 5 mW. It is shown that the proposed transmitter meets the spectral mask, defined in the targeted IEEE 802.16e (WiMAX) standard, with a margin of 20 dB and achieves an error-vector-magnitude (EVM) performance of -36 dB with a margin of 6 dB. View full abstract»

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  • A 0.18- \mu\hbox {m} CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

    Publication Year: 2009 , Page(s): 2498 - 2510
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5213 KB) |  | HTML iconHTML  

    A fully integrated 2-MHz Gaussian frequency-shift keying (GFSK) analog front end for low-IF receivers is presented. The analog GFSK demodulation uses a Bessel-based quadrature discriminator and a differentiator-based data decision circuit, eliminating the need for analog-digital converters while enabling high sensitivity and large frequency offset tolerance. The analog front end consists of a fifth-order Butterworth low-pass prefilter, a seven-stage limiter, a quadrature discriminator with a fourth-order Bessel phase-shift network, a fourth-order Butterworth low-pass postfilter, and a differentiator-based data decision circuit. The prefilter, Bessel phase shifter, postfilter, and differentiator are built using identical Gm-C cells and tuned across process variations with a single master-slave phase-locked loop. The GFSK analog front end is implemented in a 1.8-V 0.18-mum CMOS process, recovering 1-Mb/s input data from a 2-MHz GFSK signal with maximum frequency deviation of plusmn160-kHz, frequency offset tolerance from - 38% to +47%, and input sensitivity of -53 dBm and consuming 7 mA of current. View full abstract»

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  • A 107-pJ/bit 100-kb/s 0.18- \mu\hbox {m} Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet

    Publication Year: 2009 , Page(s): 2511 - 2518
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2219 KB) |  | HTML iconHTML  

    A novel communication system which simultaneously achieves the mobility of wireless communication and the low-power performance of wireline communication is developed with a printable sheet. By combining meter-scale wireline communication and micrometer-scale wireless capacitive-coupling communication, the proposed communication system enables multiple electronic objects scattered over tables, walls, and ceilings to communicate contactlessly with each other by establishing communication paths without cumbersome physical connections. The transceiver developed for the 20 cm times 20 cm communication sheet features a data-edge-signaling transmitter and a DC power-free pulse detector, thereby achieving the lowest energy of 107 pJ/bit at 100 kb/s in wireless communications at a distance of 60 cm in 0.18-mum CMOS. View full abstract»

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  • Design of a Solar-Harvesting Circuit for Batteryless Embedded Systems

    Publication Year: 2009 , Page(s): 2519 - 2528
    Cited by:  Papers (56)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1525 KB) |  | HTML iconHTML  

    The limited battery lifetime of modern embedded systems and mobile devices necessitates frequent battery recharging or replacement. Solar energy and small-size photovoltaic (PV) systems are attractive solutions to increase the autonomy of embedded and personal devices attempting to achieve perpetual operation. We present a battery less solar-harvesting circuit that is tailored to the needs of low-power applications. The harvester performs maximum-power-point tracking of solar energy collection under nonstationary light conditions, with high efficiency and low energy cost exploiting miniaturized PV modules. We characterize the performance of the circuit by means of simulation and extensive testing under various charging and discharging conditions. Much attention has been given to identify the power losses of the different circuit components. Results show that our system can achieve low power consumption with increased efficiency and cheap implementation. We discuss how the scavenger improves upon state-of-the-art technology with a measured power consumption of less than 1 mW. We obtain increments of global efficiency up to 80%, diverging from ideality by less than 10%. Moreover, we analyze the behavior of super capacitors. We find that the voltage across the supercapacitor may be an unreliable indicator for the stored energy under some circumstances, and this should be taken into account when energy management policies are used. View full abstract»

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  • IEEE Circuits and Systems Society Information

    Publication Year: 2009 , Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (33 KB)  
    Freely Available from IEEE
  • ISCAS 2010

    Publication Year: 2009 , Page(s): C4
    Save to Project icon | Request Permissions | PDF file iconPDF (642 KB)  
    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras