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Semiconductor Manufacturing, IEEE Transactions on

Issue 4 • Date Nov. 2009

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Displaying Results 1 - 25 of 30
  • Table of contents

    Page(s): C1 - C4
    Save to Project icon | Request Permissions | PDF file iconPDF (53 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Semiconductor Manufacturing publication information

    Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (38 KB)  
    Freely Available from IEEE
  • Special Section on the International Symposium on Semiconductor Manufacturing

    Page(s): 417 - 418
    Save to Project icon | Request Permissions | PDF file iconPDF (341 KB)  
    Freely Available from IEEE
  • Virtual Metrology Modeling for Plasma Etch Operations

    Page(s): 419 - 431
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2371 KB) |  | HTML iconHTML  

    The objective of this paper is to present the utilization of information produced during plasma etching for the prediction of etch bias. A plasma etching process typically relies on the concentration of electrically activated chemical species in a reaction chambers over time, depending on chamber pressure, gas flow rate, power level, and other chamber and wafer properties. Plasma properties, as well as equipment factors, are complex and vary over time. In this paper, we will use various statistical techniques to address challenges due to the nature of plasma data: high dimensionality, colinearity, parameter interactions and nonlinearities, variation of data structure due to equipment condition changing over time, etc. The emphasis will be data integrity, variable selection, accommodation for process dynamics, and model-building methods. Different techniques will be evaluated with an industrial dataset. View full abstract»

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  • Prevention of Copper Interconnection Failure in System on Chip Using Virtual Metrology

    Page(s): 432 - 437
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (745 KB) |  | HTML iconHTML  

    This paper describes copper interconnection failure in a damascene process of a system on chip (SoC) caused by plating bath degradation in copper electroplating equipment. The physical analysis using cross-sectional transmission electron microscopy revealed the failure was caused by a void in a via-hole. By using equipment engineering system (EES) data of many variables in the equipment and some statistical methods, we clarified that the root cause in the interconnection failure is plating bath degradation, which denotes the increase in a byproduct, whose existence is confirmed by analyzing the plating bath using high-performance liquid chromatography (HPLC). More detailed HPLC analysis reveals that the byproduct, which is generated by decomposing a suppressor that is one of the additives, has lighter molecule weight than that of the suppressor. Therefore, the byproduct generated by the degradation in the plating bath causes void formation in a via-hole and causes interconnection failure. We also developed a virtual metrology (VM) model for the bath plating degradation due to the byproduct generation using a mathematical model. By performing VM fault detection and classification with the mathematical model, the interconnection failure was completely prevented without the increase in the manufacturing cost due to additional inspection. View full abstract»

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  • Defect Reduction in ArF Immersion Lithography Using Particle Trap Wafers With CVD Thin Films

    Page(s): 438 - 442
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (582 KB) |  | HTML iconHTML  

    Particle trap wafers were applied to ArF immersion lithography to reduce the immersion-related defectivity. Interfacial free energy (gammaA-particle) and work of adhesion (WA-particle) between particle trap wafers and particles in immersion water explain the potential of trapping particles by the particle trap wafers. It was found that the treated SiCN chemical vapor deposition wafer performed well as a particle trap wafer and can help defect reduction in immersion lithography. View full abstract»

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  • Focus and CD Control by Scatterometry Measurements for 65/45 nm Node Devices

    Page(s): 443 - 451
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1900 KB) |  | HTML iconHTML  

    A method using scatterometry for simultaneous focus and critical dimension (CD) control method has been developed. Our focus and CD measurement method uses a five-layer scatterometry model and provides stable focus measurement when the exposure dose fluctuates. We utilize this feature and consider applying it to the response surface methodology model for focus and CD control. This control optimizes focus and calculates the correct dose allowing for the focus effect. We have confirmed that this method controls photoresist shape accurately and reduces the CD variation for 65 nm devices by 80%. View full abstract»

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  • A Novel Filter Rating Method Using Less Than 30-nm Gold Nanoparticle and Protective Ligand

    Page(s): 452 - 461
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1700 KB) |  | HTML iconHTML  

    This paper describes a novel filter rating method beyond the current 30-nm limit by combining dynamic light scattering and inductively coupled plasma mass spectrometer technique and proposes the use of gold nanoparticle as the standard challenge particle. Furthermore, the effect of protective ligand addition is investigated in order to decrease the adsorbing effect between gold nanoparticle and membrane surface. View full abstract»

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  • Behavior of Particles Reflected by Turbo Molecular Pump in Plasma Etching Apparatus

    Page(s): 462 - 467
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1648 KB) |  | HTML iconHTML  

    The behavior of particles that are reflected in a turbo molecular pump is investigated by measuring particle trajectories and the number of particles that fall on a wafer in a plasma etching apparatus. Some scattered particles collide with the wafer at high velocity, which damage fine patterns of the photoresist on the wafer. Particle contamination can be reduced by supplying carrier gas to form a down-flow when the etching plasma is not discharged. During plasma discharge, the number of particles that fall on the wafer decreases because particles are trapped near the plasma-sheath boundary. The down-flow gas reduces particle contamination by 90% through the etching sequence, including wafer transfer. View full abstract»

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  • Novel Single-Wafer Single-Chamber Dry and Wet Hybrid System for Stripping and In Situ Cleaning of High-Dose Ion-Implanted Photoresists

    Page(s): 468 - 474
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2231 KB) |  | HTML iconHTML  

    There is increasing demand for moving from batch immersion tools to single-wafer spin tools for silicon wafer cleaning, etching, and photoresist/residue removal in advanced semiconductor manufacturing. However, high-dose ion-implanted photoresist removal using a conventional single-wafer spin tool is very difficult. We have developed a novel single-wafer single-chamber dry and wet hybrid system in combination with dry ashing and moderate-temperature wet-cleaning treatments by implementing an atmospheric-pressure plasma unit into a conventional single-wafer spin cleaning tool. This compact single-wafer single-chamber system can completely remove the hardened photoresist due to high-dose ion-implantation by an atmospheric-pressure plasma ashing process followed by an in situ wet chemical process in the same single chamber within 2 min. This single-wafer single-chamber dry/wet hybrid system offers less than 1/3 smaller footprint, less than 1/4 shorter cycle time (for 50 wafer processing), and potentially better process control and less contamination risk, as well as lower equipment cost, compared to the conventional combination of two separate dry- and wet-processing systems. View full abstract»

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  • Spike Annealing as Second Rapid Thermal Annealing to Prevent Pure Nickel Silicide From Decomposing on a Gate

    Page(s): 475 - 481
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1961 KB) |  | HTML iconHTML  

    To create a nickel-monosilicide (NiSi) film with superior electrical properties, two-step rapid thermal annealing (RTA) was optimized. Using in situ chemical dry cleaning and increasing initial RTA temperature makes it possible to macroscopically transform nickel into NiSi without causing oxygen contamination. Nevertheless, di-nickel silicide (Ni2Si) remaining on the top surface of NiSi on p+-doped gate degrades the electrical properties of the NiSi film. This top-surface Ni 2Si is formed by decomposition of NiSi by conventional second RTA and appears as a disconnection of the NiSi film on the logic test device or agglomeration of silicon and nickel on the blanket NiSi film with activation energy of 2.92 eV. Using ldquospike RTArdquo with higher temperature suppresses the decomposition of NiSi and activates transformation of Ni2 Si to NiSi. It is concluded that the proposed two-step RTA significantly improves the uniformity of the electrical properties of NiSi in 65-nm-node logic devices. View full abstract»

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  • Highly Accurate Management in Dynamically Changing Fab

    Page(s): 482 - 490
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1811 KB) |  | HTML iconHTML  

    Semiconductor fab capability improvement is usually discussed in the context of static conditions. This paper focuses on a rapidly changing fab in the midst of capability improvement and describes the fab operations that maximize throughput while maintaining the cycle time in such a dynamic environment. Turn and Move are defined as parameters that indicate daily operation performance. The manufacturing process is divided into several segments, where the Turn is maintained uniformly in each segment while the increased Move capability is sequentially allocated and shifted from one segment to the next, from input side to output side of the manufacturing process. The effectiveness of this method has been demonstrated in a NOR flash memory fab. View full abstract»

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  • In-line Inspection Impact on Cycle Time and Yield

    Page(s): 491 - 498
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB) |  | HTML iconHTML  

    The semiconductor industry constantly drives for high yield and low cycle time (CT), while most current manufacturing practices consider them separately. This research investigates and exhibits the relationship between CT and yield as affected by in-line metrology inspections of production lots. Among the various factors that impact the tradeoff between CT and yield, we focus on single operation monitors and investigate their measure rate and scheduling. The research assumes a simplified production cell consisting of three operation steps that represent a typical segment in a production line. We compose and apply dynamic policies for metrology inspections via simulation and analytical methods. The aim is to concurrently reduce the CT accumulated and increase the yield achieved due to inspections. Ten inspection policies are compared under nine different operation scenarios. The results of most of the policies present a concave curve of yield versus CT. The curve illustrates that growing inspection rate increases both yield and CT until the yield reaches a maximum and then starts to decline. The cause for the yield decline is longer delay in corrective feedback to an out-of-control production tool due to longer waiting time for inspection. A cost-benefit CT-yield objective function is defined and demonstrates that the newly composed dynamic inspection policies are superior to the commonly used fixed measure rate policy. Future research could relax part of the simplified production cell assumptions in order to consider more realistic model structure and scenarios. View full abstract»

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  • Benchmarking the Productivity of Photomask Manufacturers

    Page(s): 499 - 506
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1196 KB) |  | HTML iconHTML  

    A survey-based, empirical study that benchmarks the productivity of photomask manufacturers has led to some significant conclusions. First, the wide variation in the productivity indicators from company to company suggests that all participants may have significant cost-reduction opportunities within their operations. Second, the high downtime of pattern generation tools is limiting productivity. Third, producing smaller feature sizes is correlated to an investment in engineering and experimentation capacity. It could not be confirmed that photomask manufacturers are successfully taking advantage of economies of scale, suggesting that the outlook for profitability of many photomask manufacturers is precarious. View full abstract»

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  • Threaded EWMA Controller Tuning and Performance Evaluation in a High-Mixed System

    Page(s): 507 - 511
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (455 KB) |  | HTML iconHTML  

    The exponentially weighted moving average (EWMA) controller is a very popular run-to-run (RtR) control scheme in the semiconductor industry. However, in any typical step of semiconductor process, many different products are produced on parallel tools. RtR control is usually implemented with a ldquothreadedrdquo control framework, i.e., different controllers are used for different combinations of tools and products. In this paper, the problem of EWMA controller tuning and performance evaluation in a mixed product system are investigated by simulation and time-series analysis. It was found that as the product frequency changed, the tuning guidelines of a threaded EWMA controller were different for different types of tool disturbances. For a stationary ARMA(1,1) noise, the tuning parameter lambda should be decreased as product frequency decreases. If the tool exhibits nonstationary tool dynamics, e.g., ARIMA(1,1,1) noise, the tuning parameter should increase as the product frequency decreases. View full abstract»

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  • Statistical and Experimental Analysis of Correlated Time-Varying Process Variables for Conditions Diagnosis in Chemical–Mechanical Planarization

    Page(s): 512 - 521
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3796 KB) |  | HTML iconHTML  

    During chemical-mechanical planarization (CMP) of semiconductor wafers, chemical and mechanical process variables are strongly correlated and jointly affect polishing performance. The correlation among these process variables could potentially be utilized to characterize process conditions for the purpose of diagnosis. However, process variables measured during CMP, such as the temperature distribution and coefficient of friction between wafer and pad, vary with time and present in a functional form. This significantly increases the complexity of analyzing correlation patterns and relating them with process conditions. The focus of this paper is therefore twofold: 1) experimental investigation of the correlation between sensing process variables and the implication of correlation pattern changes on process conditions and 2) statistical analysis of correlation patterns between process variables in functional form. In the designed CMP experiment, we investigated two failure modes during CMP process: pad failure and slurry failure. Slurry failure was generated by reducing the percentage of oxidizer to investigate its effects on polishing performance and heat generation on the pad. Pad failure was due to variation of diamond abrasive sizes in the conditioner. The post-CMP study of nonuniformity and defects such as scratches on the wafer was conducted to characterize process conditions. The experimental and statistical results support the investigation of correlation among process variables for condition diagnosis. View full abstract»

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  • Recipe-Independent Indicator for Tool Health Diagnosis and Predictive Maintenance

    Page(s): 522 - 535
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1757 KB) |  | HTML iconHTML  

    Advanced sensor and information technologies have made real-time tool data readily accessible to tool and process engineers. A significant number of tool parameters (status variable identifications) are collected during wafer processing, and a large amount of tool data is acquired and available for fault detection and classification (FDC). Many IC makers have substantially improved the process capabilities by implementing FDC. With the real-time tool data, one can also evaluate the overall tool condition so that tool maintenance can be more effectively scheduled and the post-maintenance tool condition can be more easily qualified. However, due to the frequent change of recipes and the diversity of operations, the overall tool health is very difficult to evaluate. In this paper, we propose a recipe-independent health indicator based on the generalized moving variance. It is shown that the indicator faithfully reveals the tool condition regardless of recipe/operation changes. With the tool health indicator, possible tool faults can be identified and proper maintenance measures can be scheduled accordingly. The proposed indicator will be demonstrated and validated through the case studies of a plasma-enhanced chemical vapor deposition and a physical vapor deposition tool from a local fab. View full abstract»

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  • A General Yield Model From Design to Product Engineering

    Page(s): 536 - 543
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1184 KB) |  | HTML iconHTML  

    This paper proposes a yield model for integrated circuits that includes the impact of design measures for robust design as well as traditional defect density parameters. This model is a powerful extension to common practice at silicon foundries and integrated device manufacturers. It is suitable for big digital designs, medium communication chips with analog parts, and just as well small circuits with nonvolatile memories. A new formula for parametric yield combining worst-case distance (WCD) and process capability indices enhances the conventional approach. A special yield part is introduced to account for the increasing relevance of lithography yield loss. The different parts are based on a common mathematical relation combining macroscopic and microscopic view. Simple learning functions are used for yield prognosis. The model has been implemented successfully for CMOS and embedded nonvolatile memory processes. Examples with measured yields demonstrate application and forecast quality. View full abstract»

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  • A Novel Approach to Link Process Parameters to BSIM Model Parameters

    Page(s): 544 - 551
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1076 KB) |  | HTML iconHTML  

    In this paper, we demonstrate a methodology to link process parameters to BSIM model parameters. Here, we have combined well-known statistical methods like principal component analysis (PCA), design of experiments (DOE), and response surface methodology (RSM) to bridge the missing link between process parameters and model parameters. The proposed methodology uses the concept of a correlation matrix, which transforms the process level information to the device and circuit level information through the BSIM model parameters. The proposed methodology has been successfully implemented on an advanced CMOS process. Our results show a strong linear correlation for the data obtained from two techniques namely TCAD technique and the standard HSPICE simulation technique. In both cases the process conditions were kept identical for comparison. View full abstract»

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  • Impact of Guardband Reduction On Design Outcomes: A Quantitative Approach

    Page(s): 552 - 565
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1721 KB) |  | HTML iconHTML  

    The value of guardband reduction is a critical open issue for the semiconductor industry. For example, due to competitive pressure, foundries have started to incent the design of manufacturing-friendly ICs through reduced model guardbands when designers adopt layout restrictions. The industry also continuously weighs the economic viability of relaxing process variation limits in the technology roadmap (available: http://public.itrs.net). Our work gives the first-ever quantification of the impact of model guardband reduction on outcomes from the synthesis, place and route (SP&R) implementation flow. We assess the impact of model guardband reduction on various metrics of design cycle time and design quality, using open-source cores and production (specifically, ARM/TSMC) 90- and 65-nm libraries and technologies as well as an industrial embedded processor core implemented in 45 nm. Our experimental data clearly shows the potential design quality and turnaround time benefits of model guardband reduction. For example, in our open-source cores, on average we observe 13% standard-cell area reduction, 12% routed wirelength reduction, 13% dynamic power reduction and 19% leakage power reduction as the consequence of a 40% reduction in library model guardband; 40% is the amount of guardband reduction reported by IBM for a variation-aware timing methodology. For the embedded processor core we observe up to 8% standard-cell area reduction, 7% routed wirelength reduction, 5% dynamic power reduction, and 10% leakage power reduction at 30% guardband reduction. We also report a set of fine-grain SPICE simulations that accurately assesses the impact of process guardband reduction, as distinguished from overall guardband reductions, on yield. We observe up to 4% increase in number of good dies per wafer at 27% process guardband reduction (i.e., with fixed voltage and temperature). Our results suggest that there is justification for the design, EDA and process communities to enabl- - e guardband reduction as an economic incentive for manufacturing-friendly design practices. View full abstract»

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  • A Novel Approach to Analyze and Model Feature Size Effects in CMP

    Page(s): 566 - 571
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (638 KB) |  | HTML iconHTML  

    In order to characterize and model the pitch dependency of the step-height decay in a typical oxide CMP process, we measured surface profiles for line-space patterns at 50% density but different pitches. The profiles are analyzed in the spatial frequency domain. For long polishing times, we find a linear dependency between the exponential decay rate and the spatial frequency. From this observation, we derive a simple mathematical model to calculate the post-CMP topography based on the layout density. Application to a typical DRAM metalization layer shows remarkably good qualitative agreement with an error in the predicted heights of plusmn15 nm. View full abstract»

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  • Polarization Effect in Laser Processing of Fine Pitch Link Structures for Advanced Memory Designs

    Page(s): 572 - 578
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (932 KB) |  | HTML iconHTML  

    Metal fuses for laser redundant links have been widely used for years in laser repair application to enhance yield. Shrinking design rules in IC fabrication have necessitated decreased fuse pitches in the redundancy circuitry. Current infrared lasers are facing the 2 mum pitch barrier due to the diffraction limited spot size and depth of focus capabilities. In this paper, we present experimental results showing how we have achieved successful laser cut processes of future metal fuse structures down to 1.0 mum pitch using a combination of the small spot of short wavelength laser and the polarization effect to tightly pitched neighbor structures. Inline polarization with link length minimizes the adjacent link damages and thus improves the energy process window for robust cutting. Electrical measurement data of metal link structures with various pitches, metal width and top passivation thicknesses shows the importance of controlling of top oxide thickness on the fine pitch structure. This enabling technology provides a viable production solution for laser fuse processing down to 45-nm node technology and below. View full abstract»

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  • Onset of Material Alterations Due to Laser-Induced Plasma Exposure in Nanofilms Deposited on Photomasks

    Page(s): 579 - 586
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2868 KB) |  | HTML iconHTML  

    Damage-free removal of sub-100 nm particles from photomasks with deposited nanofilms is a challenge in lithography. Laser-induced plasma (LIP) is an emerging noncontact, chemical-free, dry, and selective nanoparticle removal technique. Investigation of the onset of material alterations on bonded nanofilms for optimizing LIP particle removal process is the objective of this paper. Shockwave thermomechanical excitation and radiation heating from the plasma core are major potential sources of damage. Computational analyses reported here indicate radiation heating as the chief damage source. Damage thresholds for the critical nanofilm surface temperature rise and radial stress component have been identified for a given nanosecond pulsed laser. View full abstract»

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  • Use of Surface Haze for Evaluation of Photoresist Residue Removal Efficiency

    Page(s): 587 - 591
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1688 KB) |  | HTML iconHTML  

    A new method for the fast evaluation of photoresist residue removal efficiency is discussed in this paper. In this method ldquohazerdquo which is the low-frequency component of the background signal of a light scattering instrument is mapped over the entire wafer. Since the background signal is sensitive to any kind of surface anomaly, it can be used as a metrology for any kind of surface roughness or residues. The goal of this paper is to devise a fast and cheap screening method for photoresist residue removal efficiency. Using this method we show that cleaning solutions can be easily screened for their residue removal efficiencies based on the haze signal of the light scattering instrument. View full abstract»

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  • Fracture Toughness Assessment of Patterned Cu-Interconnect Stacks by Dual-Cantilever-Beam (DCB) Technique

    Page(s): 592 - 595
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (855 KB) |  | HTML iconHTML  

    Dual cantilever beam (DCB) mechanical testing is applied to two kinds of chips, manufactured in the 45 nm technology node. Both chips consist of different numbers of ultra low-k (ULK) dielectric layers, however, they have similarly designed crack-stop structures. It is shown that in all cases, cohesive cracking occurred in the upper ULK layers. The crack-stops hamper the crack propagation, and cracks are deflected outside the interconnect stack. The paths of the deflected crack fronts are FIB-sectioned and imaged in SEM. The increasing number of ULK layers leads to decrease in effective Gc of the stack. View full abstract»

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721