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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 10 • Date Oct. 2009

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Displaying Results 1 - 16 of 16
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Page(s): C2
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  • Analytical Settling Noise Models of Single-Loop Sigma–Delta ADCs

    Page(s): 753 - 757
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (475 KB) |  | HTML iconHTML  

    Switched-capacitor integrators are the basic building components for sigma-delta (SigmaDelta) modulators, and their incomplete charge transfer (settling problem) constitutes one of the dominant error sources in SigmaDelta modulators. Due to the complexity of the settling problem, analytic models for related noises are nonexistent. In this brief, closed forms of settling error models are obtained and represented as functions of SigmaDelta modulator system parameters. Both behavioral simulations and transistor-level circuit simulations are employed to verify these analytical models, and the results show that our analytical models are sufficiently accurate. View full abstract»

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  • Single-Capacitor Active-Feedback Compensation for Small-Capacitive-Load Three-Stage Amplifiers

    Page(s): 758 - 762
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (305 KB) |  | HTML iconHTML  

    This brief presents a single-capacitor active-feedback compensation (SCAFC) scheme for three-stage internal amplifiers driving small capacitive loads. The proposed SCAFC scheme can stabilize the three-stage amplifier by using only a single small-value compensation capacitor, thereby significantly reducing the amplifier implementation area. With the small-value compensation capacitor, the wide gain-bandwidth product (GBW) of the SCAFC amplifier can also be achieved under low-power conditions. Implemented in a standard 0.35-mum CMOS process, the proposed three-stage SCAFC amplifier achieves over 100-dB dc gain, 9.6-MHz GBW, and 6.1-V/mus average slew rate, by only dissipating 90 muW at 1.5 V and using a 1-pF compensation capacitor, when driving a 500-kOmega // 20-pF load. The proposed SCAFC amplifier experimentally improves both bandwidth-to-power and slew-rate-to-power efficiencies by more than 14 times and 9 times, respectively, as compared to a conventional three-stage nested-Miller-compensated amplifier. View full abstract»

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  • High-Efficiency Current-Regulated Charge Pump for a White LED Driver

    Page(s): 763 - 767
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (266 KB) |  | HTML iconHTML  

    This brief presents a high-efficiency current-regulated charge pump for a white light-emitting diode driver. The charge pump incorporates no series current regulator, unlike conventional voltage charge pump circuits. Output current regulation is accomplished by the proposed pumping current control. The experimental system, with two 1-muF flying and load capacitors, delivers a regulated 20-mA current from an input supply voltage of 2.8-4.2 V. The measured variation is less than 0.6% at a pumping frequency of 200 kHz. The active area of the designed chip is 0.43 mm2 in a 0.5-mum CMOS process. View full abstract»

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  • Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver

    Page(s): 768 - 772
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (367 KB) |  | HTML iconHTML  

    Two approaches to calibrate a pipelined analog-to-digital converter (ADC) and adapt an equalizer in a baseband receiver are proposed. Adaptive digital correction is used to calibrate the weights applied to the ADC output decisions so that the mean square error across the slicer in the receiver is minimized. Simulation results are presented to demonstrate the joint calibration of a pipelined ADC and adaptation of a channel equalizer. View full abstract»

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  • A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays

    Page(s): 773 - 777
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1103 KB) |  | HTML iconHTML  

    A wide-range fast-locking embedded clock receiver, which can provide a continuous data rate of 140 Mb/s to 1.82 Gb/s in a 0.25-mum CMOS process, is presented. A fast lock time of 7.5 mus and a small root-mean-square jitter of 15 ps are achieved by using the proposed frequency-band selection and frequency acquisition schemes, as well as a simple linear-phase detector. The implemented embedded clock receiver occupies 2.00 mm2 and consumes currents of 44 and 137 mA at 140 Mb/s and 1.82 Gb/s, respectively, including input/output currents. View full abstract»

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  • Impact of Deep-Trench-Isolation-Sharing Techniques on Ultrahigh-Speed Digital Systems

    Page(s): 778 - 782
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (507 KB) |  | HTML iconHTML  

    In the past, the large area of heterojunction bipolar transistors (HBTs) in silicon germanium (SiGe) bipolar complementary metal-oxide-semiconductor (BiCMOS) processes has prevented them from being widely used in ultrahigh-speed digital systems. The consequent longer interconnects among HBTs also offset the speed advantage of HBTs. In this brief, four deep trench isolation sharing (DTIS) methods are proposed to significantly reduce the HBT layout area. The 2 × 2 HBT layout area can be reduced by 20%-42%, and large-scale HBT system layouts can be reduced by 24%-48% or even further. Two IBM 0.18- mum SiGe 7HP chips based on Xilinx 6200 digital configurable logic blocks (CLBs) and logic cells were fabricated for verification. The maximum difference between measurement and postlayout simulation is 6.1%. Compared with the traditional layout implementation, the DTIS layout improved the system speed by 22% due to shorter interconnects among HBTs. View full abstract»

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  • A 50-Gb/s 10-mW Analog Equalizer Using Transformer Feedback Technique in 65-nm CMOS Technology

    Page(s): 783 - 787
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1047 KB) |  | HTML iconHTML  

    A 50-Gb/s low-power analog equalizer has been realized in 65-nm CMOS technology. This equalizer adopts the proposed transformer feedback technique to achieve a peaking gain of 18 dB at 25 GHz and low-power dissipation. The whole equalizer without the output buffer consumes 10 mW from a 1-V supply. The chip occupies 0.35 times 0.27 mm2. For a 50-Gb/s pseudorandom bit sequence of 27 - 1 , the measured bit error rate is less than 10-12, and the measured maximum root-mean-square and peak-to-peak jitters are 2.7 and 12.4 ps, respectively. View full abstract»

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  • Fast Algorithm and Low-Cost Hardware-Sharing Design of Multiple Integer Transforms for VC-1

    Page(s): 788 - 792
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (809 KB) |  | HTML iconHTML  

    In this brief, the fast 1D multiple integer transforms of Windows Media Video 9 (WMV-9/VC-1) are proposed by matrix decompositions, additions, and row/column permutations. Then, the proposed fast 1D integer transforms are hardware shared, and they can be applied to the 2D transform scheme. The hardware costs of the proposed fast 1D and 2D integer transform designs are smaller than those of the previous individual designs without shares. With the hardware share, the proposed architecture is suitable for the low-cost implementation of the VC-1 codec. View full abstract»

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  • Common Architecture Design of Novel Recursive MDCT and IMDCT Algorithms for Application to AAC, AAC in DRM, and MP3 Codecs

    Page(s): 793 - 797
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (393 KB) |  | HTML iconHTML  

    This paper presents a novel recursive algorithm to compute the modified discrete cosine transform (MDCT) and the inverse MDCT (IMDCT) based on type IV of the discrete cosine transform (DCT-IV) algorithm. The proposed algorithm has the following advantages: In contrast with parallel designs, the input sequence fed by serial in/serial out (SISO) can dynamically be switched with the variable window length. The data throughput per transformation for the MDCT and IMDCT algorithms is four times higher than that of the previous algorithms, and the ROM size can be reduced by 50%-79%. Less memory is required for accessing; thus, it can reduce the chip area in hardware implementation. The chip efficiency is also increased, and the proposed architecture makes a feasible design to integrate several audio standards [i.e., advanced audio coding (AAC)/AAC in digital radio mondiale (DRM/MPEG-1 Audio Layer 3 (MP3)] into one portable media player. The proposed algorithm is designed and fabricated by using 0.18-mum 1P6M complimentary metal-oxide-semiconductor (CMOS) process. The core area is 441 times 437 mum2, including the MDCT, IMDCT, and DCT-IV modules. For modern audio applications, i.e., AAC/AAC in DRM/MP3, this processor only consumes 14.077/3.482/0.3138 mW at 50/12.5/1 MHz. Furthermore, the proposed algorithm can calculate the 2048/1920/256/240/36/12-point MDCT and the 1024/960/128/120/18/6-point IMDCT. View full abstract»

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  • A New Stability Criterion for a Partial Element Equivalent Circuit Model of Neutral Type

    Page(s): 798 - 802
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (183 KB) |  | HTML iconHTML  

    This brief is concerned with stability for a partial element equivalent circuit model of neutral type. First, the relationship between two recently established integral inequalities is presented. Second, a new Lyapunov-Krasovskii functional is introduced based on the fact that the delay interval is nonuniformly divided into multiple subintervals, and different functionals are chosen on different subintervals. Then, some new delay-dependent criteria are derived. Finally, a numerical example is given to show that the results obtained by the new stability criteria can significantly improve some existing results. View full abstract»

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  • 2010 IEEE International Symposium on Circuits and Systems (ISCAS2010)

    Page(s): 803
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Page(s): 804
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  • IEEE Circuits and Systems Society Information

    Page(s): C3
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  • Blank page [back cover]

    Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope