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IEEE Design & Test of Computers

Issue 5 • Sept.-Oct. 2009

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Displaying Results 1 - 23 of 23
  • [Front cover]

    Publication Year: 2009, Page(s): c1
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  • Front Covers 
  • Table of Contents

    Publication Year: 2009, Page(s): c2
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  • Toc 
  • Departments [Table of Contents]

    Publication Year: 2009, Page(s): 1
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  • Stacking chips in 3D

    Publication Year: 2009, Page(s): 2
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  • [Masthead]

    Publication Year: 2009, Page(s): 3
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  • Guest Editors' Introduction: Opportunities and Challenges of 3D Integration

    Publication Year: 2009, Page(s):4 - 5
    Cited by:  Papers (3)
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  • Opportunities and Challenges for 3D Systems and Their Design

    Publication Year: 2009, Page(s):6 - 14
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1627 KB) | HTML iconHTML

    This article presents the system design opportunities offered by 3D integration, and it discusses the design and test challenges for 3D ICs, with various new design-for-manufacture and DFT issues. View full abstract»

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  • Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity

    Publication Year: 2009, Page(s):15 - 25
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2293 KB) | HTML iconHTML

    This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs-based method to optimize the power grid design. We explore the trade-offs between MIM decaps and traditional CMOS dec... View full abstract»

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  • Test Challenges for 3D Integrated Circuits

    Publication Year: 2009, Page(s):26 - 35
    Cited by:  Papers (175)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB) | HTML iconHTML

    One of the challenges for 3D technology adoption is the insufficient understanding of 3D testing issues and the lack of DFT solutions. This article describes testing challenges for 3D ICs, including problems that are unique to 3D integration, and summarizes early research results in this area. Researchers are investigating various 3D IC manufacturing processes that are particularly relevant to tes... View full abstract»

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  • 3D DRAM Design and Application to 3D Multicore Systems

    Publication Year: 2009, Page(s):36 - 47
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1180 KB) | HTML iconHTML

    From a system architecture perspective, 3D technology can satisfy the high memory bandwidth demands that future multicore/manycore architectures require. This article presents a 3D DRAM architecture design and the potential for using 3D DRAM stacking for both L2 cache and main memory in 3D multicore architecture. View full abstract»

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  • Mixed-Signal Production Test: A Measurement Principle Perspective

    Publication Year: 2009, Page(s):48 - 62
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (982 KB) | HTML iconHTML

    This article, based on a tutorial the author presented at ITC 2008, is an overview and introduction to mixed-signal production test. The article focuses on the fundamental techniques and procedures in production test and explores key issues confronting the industry. View full abstract»

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  • Call for Papers

    Publication Year: 2009, Page(s): 63
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  • Statistics in Semiconductor Test: Going beyond Yield

    Publication Year: 2009, Page(s):64 - 73
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1011 KB) | HTML iconHTML

    The quantity and complexity of data generated at each test manufacturing step can be daunting. This article, which emerged from a tutorial presented at ITC 2008, explains the application of statistics to help process that data and provides examples of how test has shifted from descriptive to predictive methods. View full abstract»

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  • Multidimensional Test Escape Rate Modeling

    Publication Year: 2009, Page(s):74 - 82
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (435 KB) | HTML iconHTML

    Today's SoC designs contain many types of circuitry, each with various test types. This article revisits the classic test escape models and highlights their limitations in a test environment with different types of circuits and different test types with overlapping coverage. A new methodology for test escape rate prediction is presented. View full abstract»

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  • A Generic Virtual Bus for Hardware Simulator Composition

    Publication Year: 2009, Page(s):83 - 91
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (165 KB) | HTML iconHTML

    The typical interface between hardware components is a standardized bus. This article presents a virtual counterpart for simulated hardware components: a virtual bus on a virtual motherboard. The authors show that reuse of standard components, common with real hardware, can find its analogy in the domain of simulated hardware, making simulators less expensive and more flexible. View full abstract»

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  • Robust On-Chip Signaling by Staggered and Twisted Bundle

    Publication Year: 2009, Page(s):92 - 104
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1286 KB) | HTML iconHTML

    Existing shield insertion for multiple signal nets can lead to a nonuniformly distributed, capacitive-coupling length and inductive return paths, introducing large delays and delay variation by crosstalk. This article discusses a twisted, staggered interconnect structure that reduces both inductive and capacitive crosstalk. The proposed design reduces delay by 25% and reduces delay variation by 25... View full abstract»

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  • Test Technology TC Newsletter

    Publication Year: 2009, Page(s): 105
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  • Teaching someone to fish (review of Computers as Components: Principles of Embedded Computing System Design, 2nd ed. by Wayne Wolf; 2008) [Book reviews]

    Publication Year: 2009, Page(s):106 - 107
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  • CEDA Currents

    Publication Year: 2009, Page(s):108 - 110
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  • Design Automation Technical Committee Newsletter

    Publication Year: 2009, Page(s): 111
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  • The fate of stacking

    Publication Year: 2009, Page(s): 112
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (66 KB) | HTML iconHTML

    The impending doom of CMOS scaling has semiconductor mavericks scrambling for alternative solutions to continue increasing the device density per chip. One serious candidate is 3D integration in which the planar manufacturing technology extends skyward into the third dimension, much like skyscrapers. Similarities between chip architecture and building architecture are plentiful, and the author dra... View full abstract»

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  • [Advertisement - Back cover]

    Publication Year: 2009, Page(s): c3
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  • [Advertisement - Back cover]

    Publication Year: 2009, Page(s): c4
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty