# IEEE Journal of Solid-State Circuits

## Filter Results

Displaying Results 1 - 25 of 30
• ### [Front cover]

Publication Year: 2009, Page(s):C1 - C4
| |PDF (46 KB)
• ### IEEE Journal of Solid-State Circuits publication information

Publication Year: 2009, Page(s): C2
| |PDF (40 KB)

Publication Year: 2009, Page(s):2625 - 2626
| |PDF (46 KB)
• ### Introduction to the Special Section on the IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS 2008)

Publication Year: 2009, Page(s):2627 - 2628
| |PDF (420 KB) | HTML
• ### High-Efficiency WCDMA Envelope Tracking Base-Station Amplifier Implemented With GaAs HVHBTs

Publication Year: 2009, Page(s):2629 - 2639
Cited by:  Papers (61)  |  Patents (8)
| |PDF (1853 KB) | HTML

A record high-performance GaAs high-voltage HBT (HVHBT)-based WCDMA base-station power amplifier is presented, which uses an envelope tracking bias system to achieve high efficiency and linearity. A wideband envelope amplifier provides dynamic collector supply biasing to the RF stage. A digital pre-distortion technique is employed to satisfy the linearity specifications of WCDMA. The measured over... View full abstract»

• ### A Wideband Power Amplifier MMIC Utilizing GaN on SiC HEMT Technology

Publication Year: 2009, Page(s):2640 - 2647
Cited by:  Papers (47)  |  Patents (8)
| |PDF (1208 KB) | HTML

The design and performance of a wideband power amplifier MMIC suitable for electronic warfare (EW) systems and other wide bandwidth applications is presented. The amplifier utilizes dual field plate 0.25- mum GaN on SiC device technology integrated into the three metal interconnect (3 MI) process flow. Experimental results for the MMIC at 30 V power supply operation demonstrate greater than 10 dB ... View full abstract»

• ### A Cool, Sub-0.2 dB Noise Figure GaN HEMT Power Amplifier With 2-Watt Output Power

Publication Year: 2009, Page(s):2648 - 2654
Cited by:  Papers (9)
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This paper reports on a S-, C-band low-noise power amplifier (LNPA) which achieves a sub-0.2 dB noise figure (NF) over a multi-octave band and a saturated output power (Psat) of 2 W at a cool temperature of -30degC . The GaN MMIC is based on a 0.2 mum AlGaN/GaN-SiC HEMT technology with an fT ~ 75 GHz. At a cool temperature of -30degC and a power bias of 15 V-400 mA, the MMIC achieves 0.... View full abstract»

• ### SiGe Bipolar VCO With Ultra-Wide Tuning Range at 80 GHz Center Frequency

Publication Year: 2009, Page(s):2655 - 2662
Cited by:  Papers (49)  |  Patents (2)
| |PDF (786 KB) | HTML

A SiGe millimeter-wave VCO with a center frequency around 80 GHz and an extremely wide (continuous) tuning range of 24.5 GHz ( ap 30%) is presented. The phase noise at 1 MHz offset is -97 dBc/Hz at the center frequency (and less than -94 dBc/Hz in a frequency range of 21 GHz). The maximum total output power is about 12 dBm. A cascode buffer improves decoupling from the output load at reasonable VC... View full abstract»

• ### 100 GHz+ Gain-Bandwidth Differential Amplifiers in a Wafer Scale Heterogeneously Integrated Technology Using 250 nm InP DHBTs and 130 nm CMOS

Publication Year: 2009, Page(s):2663 - 2670
Cited by:  Papers (8)
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Differential amplifiers incorporating the advantages of both Si and III-V technologies have been fabricated in a wafer scale, heterogeneously integrated, process using both 250 nm InP DHBTs and 130 nm CMOS. These ICs demonstrated gain-bandwidth product of 40-130 GHz and low frequency gain > 45 dB . The use of InP DHBTs supports a > 6.9 V differential output swing and a slew rate > 4 times... View full abstract»

• ### A 40 mW 3 Gb/s Self-Compensated Differential Transimpedance Amplifier With Enlarged Input Capacitance Tolerance in 0.18 $mu$m CMOS Technology

Publication Year: 2009, Page(s):2671 - 2677
Cited by:  Papers (3)  |  Patents (1)
| |PDF (454 KB) | HTML

By combining an appropriate differential-sensing scheme with the bootstrapping technique, this paper presents a self-compensated design topology which is shown to be effective at reducing the loading effects due to the photodiode and the ESD protection circuit at the differential inputs. The built-in offset creation technique is introduced to overcome voltage headroom limitation. Furthermore, the ... View full abstract»

• ### Analysis and Optimization of Current-Driven Passive Mixers in Narrowband Direct-Conversion Receivers

Publication Year: 2009, Page(s):2678 - 2688
Cited by:  Papers (89)  |  Patents (1)
| |PDF (1470 KB) | HTML

Properties of the current-driven passive mixer are explored to maximize its performance in a zero-IF receiver. Since there is no reverse isolation between the RF and baseband sides of the mixer, the mixer reflects the baseband impedance to the RF and vice versa through simple frequency shifting. It is also shown that in an IQ down-conversion system the lack of reverse isolation causes a mut... View full abstract»

• ### Noise-Shaping Gain-Filtering Techniques for Integrated Receivers

Publication Year: 2009, Page(s):2689 - 2701
Cited by:  Papers (11)  |  Patents (1)
| |PDF (1766 KB) | HTML

In this paper, a new technique for realizing area-efficient, low-noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the passband of the filter. This is illustrated by implementing a programmable noise-shaped post-mixer gain-filtering circuit for a CMOS Mobile-TV tuner. The proposed circu... View full abstract»

• ### Intermittent Operation Control Scheme for Reducing Power Consumption of UWB-IR Receiver

Publication Year: 2009, Page(s):2702 - 2710
Cited by:  Papers (8)
| |PDF (1404 KB) | HTML

A low power ultra-wideband impulse radio (UWB-IR) receiver was developed in 0.18-mum CMOS. All circuits of the receiver AFE operate intermittently with a sampling clock of an analog-digital converter (ADC). The sampling rate of the ADC is equal to the pulse repetition frequency of the received signals. Power consumption of the receiver AFE is reduced by 60% using a developed intermittent operation... View full abstract»

• ### A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas

Publication Year: 2009, Page(s):2711 - 2721
Cited by:  Papers (48)  |  Patents (1)
| |PDF (2918 KB) | HTML

A 43-GHz wireless inter-chip data link including antennas, transmitters, and receivers is presented. The industry standard bonding wires are exploited to provide high efficiency and low-cost antennas. This type of antennas can provide an efficient horizontal communication which is hard to achieve using conventional on-chip antennas. The system uses binary amplitude shift keying (ASK) modulation to... View full abstract»

• ### An All-Digital RF Signal Generator Using High-Speed $DeltaSigma$ Modulators

Publication Year: 2009, Page(s):2722 - 2732
Cited by:  Papers (51)  |  Patents (1)
| |PDF (2470 KB) | HTML

An all-digital RF signal generator using DeltaSigma modulation and targeted at transmitters for mobile communication terminals has been implemented in 90 nm CMOS. Techniques such as redundant logic and non-exact quantization allow operation at up to 4 GHz sample rate, providing a 50 MHz bandwidth at a 1 GHz center frequency. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB... View full abstract»

• ### Design Considerations for 60 GHz Transformer-Coupled CMOS Power Amplifiers

Publication Year: 2009, Page(s):2733 - 2744
Cited by:  Papers (60)
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This work discusses the design methodologies for efficient power generation at mm-wave frequencies in CMOS. Passive elements play an important role in PA design, as they determine both the output power and power gain of the circuit. In this work, we have developed a methodology for design of transformer-coupled power amplifiers. A distributed model of on-chip transformers has been developed that c... View full abstract»

• ### A 0.1 mm$^{2}$ , Wide Bandwidth Continuous-Time $SigmaDelta$ ADC Based on a Time Encoding Quantizer in 0.13 $mu$ m CMOS

Publication Year: 2009, Page(s):2745 - 2754
Cited by:  Papers (26)  |  Patents (3)
| |PDF (961 KB) | HTML

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantiza... View full abstract»

• ### A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC

Publication Year: 2009, Page(s):2755 - 2765
Cited by:  Papers (18)  |  Patents (1)
| |PDF (2341 KB) | HTML

A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 mum CMOS. The 22 MS/s ADC achieves a m... View full abstract»

• ### Adaptive Blocker Rejection Continuous-Time $Sigma Delta$ ADC for Mobile WiMAX Applications

Publication Year: 2009, Page(s):2766 - 2779
Cited by:  Papers (24)
| |PDF (3555 KB) | HTML

An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (SigmaDelta) analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures the ADC loop architecture to avoid overloading in the presence of strong interferers, improving receiver channel selectivity and sensitivity without increasing its dynamic range (DR) requirements. The adaptive operation rel... View full abstract»

• ### Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA

Publication Year: 2009, Page(s):2780 - 2789
Cited by:  Papers (25)
| |PDF (1238 KB) | HTML

To reduce power dissipation, the input sample-and-hold amplifier (SHA) is eliminated in a pipelined analog-to-digital converter (ADC) with nested background calibration. The nested architecture calibrates the pipelined ADC with an algorithmic ADC that is also calibrated. Without an input SHA, a timing difference between the sampling instants of the two ADCs creates an error that interferes with ca... View full abstract»

• ### A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-$mu$ m CMOS

Publication Year: 2009, Page(s):2790 - 2799
Cited by:  Papers (18)
| |PDF (1419 KB) | HTML

This paper presents a 100-kHz fifth-order Chebychev low-pass filter (LPF) using the proposed dynamic biasing (DB) technique which enables wide dynamic range under a low-supply voltage. The change of state variables in the internal nodes of the filter can be corrected by using a novel simplified scheme, avoiding the output transient owing to dynamic biasing. The filter, including an automatic frequ... View full abstract»

• ### A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators

Publication Year: 2009, Page(s):2800 - 2807
Cited by:  Papers (6)  |  Patents (1)
| |PDF (974 KB) | HTML

The present paper introduces a resonant clock generation and distribution scheme that uses uniform amplitude and uniform phase standing wave oscillators in order to distribute a high-frequency clock signal with low skew, low jitter, and low power. A suitable distributed resonator for a global clock distribution that is inductively loaded transmission line generating a uniform amplitude and uniform... View full abstract»

• ### A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution

Publication Year: 2009, Page(s):2808 - 2816
Cited by:  Papers (86)  |  Patents (5)
| |PDF (1306 KB) | HTML

This paper presents the design of a digital PLL which uses a high-resolution time-to-digital converter (TDC) for wide loop bandwidth. The TDC uses a time amplification technique to reduce the quantization noise down to less than 1 ps root mean square (RMS). Additionally TDC input commutation reduces low-frequency spurs due to inaccurate TDC scaling factor in a counter-assisted digital PLL. The loo... View full abstract»

• ### Resilient Self-V$_{rm DD}$-Tuning Scheme With Speed-Margining for Low-Power SRAM

Publication Year: 2009, Page(s):2817 - 2823
Cited by:  Papers (5)
| |PDF (1612 KB) | HTML

Lowering the supply voltage is an effective way to significantly reduce the power consumption of a static random access memory (SRAM). However, the minimum supply voltage (Vminf) required to support a given operating frequency in an SRAM macro is often elusive from one chip to another due to process variations. Moreover, temperature could vary when an SRAM macro is in operation, and thu... View full abstract»

• ### Capacitive Power Management Circuit for Micropower Thermoelectric Generators With a 1.4 $mu$A Controller

Publication Year: 2009, Page(s):2824 - 2833
Cited by:  Papers (49)
| |PDF (1444 KB) | HTML

Power autonomy is an important requirement for wireless sensor nodes. Thermoelectric generators can produce sufficient power for low power applications. Due to varying temperature, a power management circuit will be required. This paper presents such a power management circuit, realized in the AMIS I3T80 CMOS technology. It contains a Dickson charge pump with a variable number of stages as a DC/DC... View full abstract»

## Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Jan Craninckx
Imec
Kapeldreef 75
B-3001 Leuven, Belgium
jssc.craninckx@gmail.com