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IEEE Transactions on Computers

Issue 2 • Feb 1993

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Displaying Results 1 - 13 of 13
  • Reducing iteration time when result digit is zero for radix 2 SRT division and square root with redundant remainders

    Publication Year: 1993, Page(s):239 - 246
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    A new architecture is presented for shared radix 2 division and square root whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. The solution presented uses a redundant representation of the partial remainder, while keeping the advantages of classical solutions. It is shown how the next digit of the result can be selected even when the rem... View full abstract»

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  • Hardware efficient algorithms for trigonometric functions

    Publication Year: 1993, Page(s):235 - 239
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    A new algorithm is presented which significantly reduces the minimum amount of logic required to calculate sine, cosine, and square root. It is derived from an old method for computing certain inverse functions which was once considered for use in software, but then abandoned because of efficiency concerns. However, when reversed and combined with a restoring square root algorithm, a unique new de... View full abstract»

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  • The CORDIC algorithm: new results for fast VLSI implementation

    Publication Year: 1993, Page(s):168 - 178
    Cited by:  Papers (66)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    After a brief survey of the CORDIC algorithm, some new results that allow fast and easy signed-digit implementation of CORDIC, without modifying the basic iteration step are given. A slight modification would make it possible to use a carry-save representation of numbers, instead of a signed-digit one. The method, called the branching CORDIC method, consists of performing in parallel two classic C... View full abstract»

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  • Notes on multiple input signature analysis

    Publication Year: 1993, Page(s):228 - 234
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    Many results regarding the probability of aliasing for multiple-input compactors have been derived under error assumptions that are not very realistic for VLSI circuits. Recently, the value of aliasing probability has been proven to tend to 2-k, where k is the number of binary memory elements of the linear compactor. This result is based on the assumption that the compactor is ... View full abstract»

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  • A cube-connected cycles architecture with high reliability and improved performance

    Publication Year: 1993, Page(s):246 - 253
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    The cube-connected cycles (CCC) architecture is an attractive parallel computation network, because it is suitable for VLSI implementation while preserving all the desired features of hypercubes. However, the CCC tends to suffer from considerable performance degradation when a fault arises. In this work, a fault-tolerant CCC which exhibits significantly enhanced reliability is proposed. Reconfigur... View full abstract»

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  • A characterization of binary decision diagrams

    Publication Year: 1993, Page(s):129 - 137
    Cited by:  Papers (14)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    Binary decision diagrams (BDDs) are a representation of Boolean functions. Its use in the synthesis, simulation, and testing of Boolean circuits has been proposed by various researchers. In all these applications of BDDs solutions to some fundamental computational problems are needed. A characterization of BDDs in terms of the complexity of these computational problems is presented. A tighter boun... View full abstract»

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  • Alternative strategies for improving the fairness in and an analytical model of the DQDB network

    Publication Year: 1993, Page(s):151 - 167
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1252 KB)

    The unfairness problem of the distributed queue dual bus (DQDB) (IEEE Std 802.6) network is addressed, and several alternative solutions that can improve the network's fairness are proposed. Implementation methods that require simple additional hardware on top of the regular DQDB interface are outlined. Simulation examples are employed to compare the performance of the schemes and to gain insight ... View full abstract»

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  • Gossiping in a distributed network

    Publication Year: 1993, Page(s):253 - 256
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Consider a network in which each unit initially knows only its own identity and the identity of its immediate neighbors. Suppose each unit has a message intended for all other units. The authors give a distributed algorithm to accomplish this in point-to-point networks which is optimal in the number of transmissions it requires. They also show that this algorithm accomplishes this efficiently for ... View full abstract»

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  • An HIPPI interconnection system

    Publication Year: 1993, Page(s):138 - 150
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1072 KB)

    The proposed HIPPI standard, a connection-oriented communication standard for very-high-speed interconnection systems connecting high-end computing systems, is discussed. The problems of managing connections and of configuring the interconnection system as either a single crossbar switch or as a clique of crossbar switches are considered. Three connection management policies are introduced: a cent... View full abstract»

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  • Fault detection in CVS parity trees with application to strongly self-checking parity and two-rail checkers

    Publication Year: 1993, Page(s):179 - 189
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB)

    The problem of single stuck-at, stuck-open, and stuck-on fault detection in cascode voltage switch (CVS) parity trees is considered. The results are also applied to parity and two-rail checkers. It is shown that, if the parity tree consists of only differential cascode voltage switch (DCVS) EX-OR gates, then the test set consists of at most five vectors (in some cases only four vectors are require... View full abstract»

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  • Managing locality sets: the model and fixed-size buffers

    Publication Year: 1993, Page(s):190 - 204
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1412 KB)

    A memory-management model based on describing reference behavior in terms of locality-set sequences is proposed. Specialized for fixed-size buffers, this model is used to define the PSETMIN and SETMIN strategies which are proven to minimize the number of page faults in the presence and absence of prepaging, respectively. In contrast to MIN, they are also realizable for certain computations. The me... View full abstract»

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  • Diagnosis and repair in multiprocessor systems

    Publication Year: 1993, Page(s):205 - 217
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1136 KB)

    Diagnosis of multiprocessor systems in which faulty processors can be replaced by spares or repaired is known as sequential diagnosis. A generalization is considered of classical sequential diagnosis, referred to as diagnosis and repair, under a probabilistic model for the faults and test outcomes in a system. It is shown that correct diagnosis and repair of all faulty processors can be achieved w... View full abstract»

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  • A hybrid neural network model for solving optimization problems

    Publication Year: 1993, Page(s):218 - 227
    Cited by:  Papers (18)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    A hybrid neural network model for solving optimization problems is proposed. An energy function which contains the constraints and cost criteria of an optimization problem is derived, and then the neural network is used to find the global minimum (or maximum) of the energy function, which corresponds to a solution of the optimization problem. The network contains two subnets: a constraint network ... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org