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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct. 2009

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Displaying Results 1 - 25 of 30
  • Table of contents

    Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • Compact Modeling of the Temperature Dependence of Parasitic Resistances in SiGe HBTs Down to 30 K

    Page(s): 2169 - 2177
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1074 KB) |  | HTML iconHTML  

    In this paper, we investigate the physics and modeling of temperature dependence of various parasitic resistances in SiGe heterojunction bipolar transistors down to 30 K. Carrier freezeout is shown to be the dominant contributor to increased resistances at cryogenic temperatures for lightly-doped and moderately-doped regions, whereas the temperature dependence of the mobility is the dominant contributor to the temperature dependence of heavily-doped regions. Two incomplete ionization models, the classic model with a doping dependent activation energy and the recent model of Altermatt , are shown to underestimate and overestimate incomplete ionization rate below 100 K for intrinsic base doping, respectively. Analysis of experimental data shows that the bound state fraction factor is temperature dependent and including this temperature dependence enables compact modeling of resistances from 30 to 300 K for moderately-doped regions. For heavily-doped regions, a dual power law mobility approximation with complete ionization is shown to work well down to 30 K. An alternative approach is also presented for heavily-doped resistors which allows one to use the same model equation for all regions. View full abstract»

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  • Effects of Self-Heating on Performance Degradation in AlGaN/GaN-Based Devices

    Page(s): 2178 - 2185
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    A self-consistent electrothermal transport model that couples electrical and thermal transport equations is established and applied to AlGaN/GaN device structures grown on the following three different substrate materials: 1) SiC; 2) Si; and 3) sapphire. Both the resultant I-V characteristics and surface temperatures are compared to experimental I -V measurements and Raman spectroscopy temperature measurements. The very consistent agreement between measurements and simulations confirms the validity of the model and its numerical rendition. The results explain why the current saturation in measured I-V characteristics occurs at a much lower electric field than that for the saturation of electron drift velocity. The marked difference in saturated current levels for AlGaN/GaN structures on SiC, Si, and sapphire substrates is directly related to the different self-heating levels that resulted from the different biasing conditions and the distinctive substrate materials. View full abstract»

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  • Three-Dimensional Real-Space Simulation of Surface Roughness in Silicon Nanowire FETs

    Page(s): 2186 - 2192
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (729 KB) |  | HTML iconHTML  

    We address the transport properties of narrow gate-all-around silicon nanowires in the presence of surface-roughness (SR) scattering at the Si/SiO2 interface, considering nanowire transistors with a cross section of 3 times 3 nm2 and gate length of 15 nm. We present transfer characteristics and effective-mobility calculations based on a full 3-D real-space self-consistent Poisson-Schrodinger solver within the nonequilibrium Green's function formalism. The effect of SR is included via a geometrical method consisting in a random realization of potential fluctuations described via an exponential autocorrelation law. The influence on transfer characteristics and on low-field mobility is evaluated by comparison with the clean case and for different values of the root mean square of potential fluctuations. The method allows us to exactly account for mode-mixing and subband fluctuations and to evaluate the effect of SR up to all orders of the interaction. We find that SR scattering is mainly responsible for positive threshold-voltage shift in the low-field regime, whereas SR-limited mobility slowly depends on the linear charge density, showing the inefficiency of mode-mixing scattering mechanism for very narrow wires. View full abstract»

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  • Band-to-Band Tunneling Ballistic Nanowire FET: Circuit-Compatible Device Modeling and Design of Ultra-Low-Power Digital Circuits and Memories

    Page(s): 2193 - 2201
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1664 KB) |  | HTML iconHTML  

    Band-to-band tunneling (BTBT) nanowire FETs have been studied as a possible successor to CMOS FETs. In the literature, it has already been shown that a 1-D p+-i- n+-type semiconductor nanowire governed by a BTBT transport mechanism offers a subthreshold swing lower than the conventional limit of 60 mV/dec while maintaining a reasonable on-state performance. The concept of BTBT nanowire FETs is primitive, and the manufacturing process is nascent. In the absence of a suitable device model and/or a reliable circuit simulator, the evaluation and impact of such novel transistors are difficult to estimate. In this paper, we propose a simple complementary device model for BTBT nanowire FETs suitable for multitransistor circuit simulation and evaluate its performance in the ballistic limit. The device models so developed have been used to simulate a class digital logic circuits and dynamic memories (e.g., DRAM) to analyze their suitability in future very large scale integration design. Circuit level simulations explicitly show that the proposed p+ -i-n+-type BTBT nanowire FETs are well suited for medium throughput (approximately hundreds of kilohertz to a few tens of megahertz) ultra-low-power applications. The standby leakage power in memory and logic circuits has been found to be as low as 10-20 W due to the inherent super cutoff nature of the device. The presence of interconnect parasitics in parallel with intrinsic device capacitance severely limits the performance of digital circuits. The impact of interconnect parasitics on the performance of BTBT nanowire FETs has also been studied. View full abstract»

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  • High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

    Page(s): 2202 - 2214
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1401 KB) |  | HTML iconHTML  

    This paper presents a rigorous investigation of high-frequency effects in carbon nanotube (CNT) interconnects and their implications for the design and performance analysis of high-quality on-chip inductors. A frequency-dependent impedance extraction method is developed for both single-walled CNT (SWCNT) and multiwalled CNT (MWCNT) bundle interconnects. The method is subsequently verified by comparing the results with those derived directly from the Maxwell's equations. Our analysis reveals for the first time that skin effect in CNT (particularly MWCNT) bundles is significantly reduced compared to that in conventional metal conductors, which makes them very attractive and promising material for high-frequency applications, including high-quality (Q) factor on-chip inductor design in high-performance RF/mixed-signal circuits. It is shown that such unique high-frequency properties of CNTs essentially arise due to their large momentum relaxation time (leading to their large kinetic inductance), which causes the skin depths to saturate with frequency and thereby limits resistance increase at high frequencies in a bundle structure. It is subsequently shown that CNT-based planar spiral inductors can achieve more than three times higher Q factor than their Cu-based counterparts without using any magnetic materials or Q factor enhancement techniques. View full abstract»

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  • The Quantum and Classical Capacitance Limits of InSb and InAs Nanowire FETs

    Page(s): 2215 - 2223
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    A comparison of nanowire FETs (NWFETs) of identical geometries but operating in two different regimes, namely, the quantum capacitance (QC) and classical capacitance (CC) regimes, is presented. n-type InSb and InAs NWFETs up to ~50 nm in diameter operate in the QC limit (QCL), and the corresponding p-type NWFETs operate in the CC limit. Drive currents at a fixed gate overdrive for the n- and p-type devices are found to be well matched. Nevertheless, the p-type devices have twice the delay times, half the intrinsic cutoff frequencies, twice the power-delay products, and four to five times the energy-delay products of the n-type devices, assuming transport is ballistic. Analytical expressions are derived for the QC, the current, the charge, the power-delay product, the energy-delay product, the gate delay time, and the cutoff frequency for a single-moded device operating in the QCL. The expressions for the power-delay product, energy-delay product, and the cutoff frequency are fundamental limits for such devices. View full abstract»

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  • Implementation of Tunneling Phenomena in a CNTFET Compact Model

    Page(s): 2224 - 2231
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1157 KB) |  | HTML iconHTML  

    This paper presents the implementation of band-to-band tunneling (BTBT) mechanisms into the compact model of a conventional carbon nanotube transistor FET featuring a MOSFET-like operation. Appropriate equations enable the calculation of the BTBT current as well as the charge pileup in the channel. To ensure the model accuracy and validate the equation set, the compact model simulation results are methodically compared with nonequilibrium Green function ones. Afterward, the investigations on the BTBT effects with respect to the figures of merits of the transistor and circuit have led to draw the conclusion that their impact is of utmost importance for large-signal analog and digital circuit designs. Neglecting the BTBT phenomena lead to an underestimation of more than 50% of the gate inverter delay and to an underestimation of power consumption of 30%. Finally, tradeoff recommendations between chirality and operating bias voltage are presented. View full abstract»

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  • Compact Model of Carbon Nanotube Transistor and Interconnect

    Page(s): 2232 - 2242
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (735 KB) |  | HTML iconHTML  

    A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both I-V and C-V characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, and bias voltages. Without any iteration in model computation, the proposed model significantly enhances the simulation efficiency for large-scale design research. By benchmarking circuit performance, the optimal space of the CNT process is further localized. It is observed that for a Schottky-barrier CNT transistor with the diameter range of 1-1.5 nm, the circuit can be more than 8× faster than that of 22-nm CMOS, with the tolerance to the variation in contact materials. View full abstract»

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  • Experimental Approach and Evaluation on Dynamic Reliability of PBGA Assembly

    Page(s): 2243 - 2249
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (450 KB) |  | HTML iconHTML  

    The aim of this paper is to provide a systematic method to perform experimental test and theoretical evaluation on fatigue characteristics of plastic-ball-grid-array (PBGA) assembly under random vibration. A specified PBGA assembly which contains different structural and material parameters was manufactured. The fatigue characteristics of PBGA assembly under random vibration were tested. Manson-Coffin empirically derived formula and rain-flow algorithm were used to achieve the fatigue life of solder joints. In the meantime, the failure curve (reliability-cycle number curve) can be obtained by using Weibull distribution method when PBGA assembly is on different working situation. Finally, life prediction of corner solder balls was deduced based on three-band technology and cumulative damage index. Test results lay a basis for high-reliability design of PBGA assembly for engineering application. View full abstract»

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  • Analytical and Finite-Element Modeling of a Cross Kelvin Resistor Test Structure for Low Specific Contact Resistivity

    Page(s): 2250 - 2254
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (637 KB) |  | HTML iconHTML  

    Various test structures have been employed to determine the specific contact resistivity (rhoc) of ohmic contacts, and cross Kelvin resistor (CKR) test structures are most suitable for estimating low rhoc values. The value determined by CKRs includes error due to parasitic resistances that have been difficult to account for when rhoc is low (< 10-7 Omega ldr cm2). In this paper, an analytical technique for determining the error in measurements from CKR test structures is presented. The analytical model described for circular contacts is based on Bessel function expressions. Using several contacts of different diameter (d) with d/w les 0.4 (w is the width of the CKR arms), the parasitic resistance can be accurately accounted for by extrapolation of experimental data to d/w rarr 0. Finite-element modeling and experimental results for metal-to-silicide contacts are used to validate the analytical expressions presented. View full abstract»

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  • Analysis of Threshold Voltage Distribution Due to Random Dopants: A 100 000-Sample 3-D Simulation Study

    Page(s): 2255 - 2263
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    Using the Glasgow ldquoatomisticrdquo simulator, we have performed 3D statistical simulations of random-dopant-induced threshold voltage variation in state-of-the-art 35- and 13-nm bulk MOSFETs consisting of statistical samples of 105 or more microscopically different transistors. Simulation on such an unprecedented scale has been enabled by grid technology, which allows the distribution and the monitoring of very large ensembles on heterogeneous computational grids, as well as the automated handling of large amounts of output data. The results of these simulations show a pronounced asymmetry in the distribution of the MOSFET threshold voltages, which increases with transistor scaling. A comprehensive statistical analysis enabled by the large sample size reveals the origin of this observed asymmetry, provides a detailed insight into the underlying physical processes, and enables the statistical enhancement of simulations of random-dopant-induced threshold voltage variation. View full abstract»

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  • Strained- \hbox {Si}_{1 - x}\hbox {Ge}_{x}/\hbox {Si} Band-to-Band Tunneling Transistors: Impact of Tunnel-Junction Germanium Composition and Doping Concentration on Switching Behavior

    Page(s): 2264 - 2269
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1059 KB) |  | HTML iconHTML  

    Strained pseudomorphic Si/Si1-xGex/Si gate-controlled band-to-band tunneling (BTBT) devices have been analyzed with varying Ge composition up to 57% and p+ tunnel-junction (source) doping concentration in the 1019-1020 cm-3 range. Measurements show the impact of these parameters on the transfer and output characteristics. Measurements are compared to simulations using a nonlocal BTBT model to analyze the mechanisms of device operation and to understand the impact of these parameters on the device switching behavior. The measured characteristics are consistent with simulation analysis that shows a reduction in energy barrier for tunneling (Egeff) and a reduction in tunneling distance with increasing Ge composition and source doping concentration. Increases in the pseudomorphic layer Ge content and doping concentration of the tunnel junction produce large improvements in the measured switching-behavior characteristics (Ion, slope, turn-on voltages, and sharpness of turn-on as a function of Vds). Simulations are also performed to project the potential performance of more optimized structures that may be suitable for extremely low power applications (Vdd < 0.4 V). View full abstract»

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  • Undoped-Body Extremely Thin SOI MOSFETs With Back Gates

    Page(s): 2270 - 2276
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (913 KB) |  | HTML iconHTML  

    We present a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates. We show that short channel control improves with the application of back bias via a decrease in the electrostatic scaling length as the subthreshold charges move toward the front gate. We demonstrate that, even for undoped ETSOI devices with ~8-nm SOI thickness, the improvement in short channel control with the application of a back bias translates to 10% higher drive current, 10% shorter gate lengths, and, consequently, 20% lower extrinsic gate delay at a fixed off-state current of 100 nA/mum and a back oxide electric field of 1.5 MV/cm (0.5 MV/cm SOI field). View full abstract»

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  • Performance Enhancements in Scaled Strained-SiGe pMOSFETs With  \hbox {HfSiO}_{x}/\hbox {TiSiN} Gate Stacks

    Page(s): 2277 - 2284
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    The short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe. View full abstract»

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  • On the Experimental Determination of Channel Backscattering Characteristics—Limitation and Application for the Process Monitoring Purpose

    Page(s): 2285 - 2290
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (742 KB) |  | HTML iconHTML  

    This paper reports a generalized temperature-dependent channel backscattering extraction method that can self-consistently determine the temperature sensitivity of the low-field mobility and the critical length in nanoscale MOSFETs. Through comparing the gate voltage and temperature dependence, we have shown that assuming constant temperature sensitivity of the low-field mobility and the critical length will result in unphysical backscattering characteristics. We have also investigated the limitation in this self-consistent method and proposed guidelines for experimental extraction. Our results show that channel backscattering is increased for NMOSFETs with higher body doping and HfO2 dielectric and can be reduced for PMOSFETs when the process-induced uniaxial compressive strain technology is employed. This paper indicates that the self-consistent temperature-dependent method is competent to be routinely used in technology development for the process monitoring purpose. View full abstract»

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  • Modeling and Analysis of Parasitic Resistance in Double-Gate FinFETs

    Page(s): 2291 - 2296
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (626 KB) |  | HTML iconHTML  

    A comprehensive model is presented to analyze the three-dimensional (3-D) source-drain (S/D) resistance of undoped double-gated FinFETs of wide and narrow S/D width. The model incorporates the contribution of spreading, sheet, and contact resistances. The spreading resistance is modeled using a standard two-dimensional (2-D) model generalized to 3-D. The contact resistance is modeled by generalizing the one-dimensional (1-D) transmission line model to 2-D and 3-D with appropriate boundary conditions. The model is compared with the S/D resistance determined from 3-D device simulations and experimental data. We show excellent agreement between our model, the simulations, and experimental data. View full abstract»

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  • Analytic Model for Undoped Symmetric Double-Gate MOSFETs With Small Gate-Oxide-Thickness Asymmetry

    Page(s): 2297 - 2301
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    In this paper, an analytic model for undoped symmetric double-gate MOSFETs with small gate-oxide-thickness asymmetry is presented by virtue of a perturbation approach. Various effects on the MOSFET performance caused by small asymmetric departure from the nominal gate oxide thickness due to process variations and uncertainties are studied. This analytic solution can be used in compact models for IC designs. View full abstract»

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  • Autonomous Refresh of Floating-Body Cell due to Current Anomaly of Impact Ionization

    Page(s): 2302 - 2311
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (546 KB) |  | HTML iconHTML  

    Physics of autonomous refresh is presented, which explains the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC). Input current to the floating body and output current from the body balance to generate an unstable stationary state that is accompanied by two stable stationary ones. The current anomaly of impact ionization is essential for the instability that brings about the bistability and is realized by positive feedback where impact ionization current input increases as the body voltage increases. Experiments with charge pumping current as output show that the autonomous refresh is possible on a single-cell basis. Necessary conditions for a high-density memory to be autonomously refreshed are derived and assessed for state-of-the-art FBCs. FBC is shown in simulation to become an SRAM cell when the autonomous refresh is applied, which uses gate direct tunneling current as output. This is an SRAM cell that is theoretically expected to have the simplest structure ever reported. View full abstract»

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  • Self-Consistent SchrÖdinger–Poisson Simulations on Capacitance–Voltage Characteristics of Silicon Nanowire Gate-All-Around MOS Devices With Experimental Comparisons

    Page(s): 2312 - 2318
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (678 KB) |  | HTML iconHTML  

    We simulate room temperature capacitance-voltage characteristics of silicon (Si) nanowire gate-all-around MOS structures with radius les 10 nm using a self-consistent Schrodinger- Poisson solver in cylindrical coordinates with full treatment of the transverse quantum confinement. In this paper, we compare our simulation results with the latest capacitance measurements on single Si nanowire pMOS and nMOS devices in the subfemtofarad range. We also propose to probe the density-of-states features of the Si channel from the capacitance-voltage characteristics at room temperature measurements using dC/dV dependence and illustrate the idea by employing the latest measurements, our quantum and Medici (Synopsys) simulations, as well as a simplified analytical model. View full abstract»

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  • Effects of the Localization of the Charge in Nanocrystal Memory Cells

    Page(s): 2319 - 2326
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (385 KB) |  | HTML iconHTML  

    In this paper, we present a peculiar characteristic of nanocrystal (NC) memory (NCM) cells: The programming (P) windows measured in linear and subthreshold regions are different. A floating-gate flash memory cell with a similar structure does not show the same behavior, and the P window (PW) is independent of the current level of the extrapolation, as expected. By performing 2-D TCAD simulations, we demonstrated that this characteristic of NCM cells is due to the localization of the charge into the NCs. We investigate the correlation between the difference of the PWs in linear and subthreshold regions and the number, width, and position of the NCs. View full abstract»

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  • Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator

    Page(s): 2327 - 2334
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1196 KB) |  | HTML iconHTML  

    Based on the continuity theorem of electric displacement including interface charges, the enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices is proposed. The following three approaches for enhancing the dielectric layer electric field EI to increase the vertical breakdown voltage of a device VB,V are presented: 1) using a thin silicon layer with a high critical electric field ES,C ; 2) introducing a low-permittivity dielectric buried layer; and 3) implementing interface charges between the silicon and the dielectric layer. Considering the threshold energy of silicon epsivT, the formula of ES,C on silicon layer thickness tS is first obtained, which increases sharply with a decrease of tS, and reaches up to 141 V/mum at tS = 0.1 mum. Expressions for EI and VByV are given, which agree well with simulative and experimental results. Based on the ENDIF, the new device structures are given, and an EI value of 300 V/mum has been experimentally obtained for double-sided trench SOI. Moreover, several conventional SOI devices are explained well by ENDIF. View full abstract»

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  • A Lossy Dielectric-Ring Loaded Waveguide With Suppressed Periodicity for Gyro-TWTs Applications

    Page(s): 2335 - 2342
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1413 KB) |  | HTML iconHTML  

    A dielectric-loaded (DL) waveguide is an attractive possibility for interaction circuits with high-power sources in the millimeter-wave regime down to tenths of millimeters, particularly for gyrotron-traveling-wave-tube amplifiers (gyro-TWTs). We present results on a systematic investigation of the influence of the periodically loaded lossy dielectric on the propagation characteristics of the operating modes, which reveals that a complex mode in the periodic system can be mapped to a corresponding mode in an empty waveguide or a uniform DL waveguide. Dielectric losses not only induce modal transitions between different modes with similar field structures and close phase velocities in the uniform system but also unify the discrete mode spectrum into a continuous spectrum in the periodic system. Since the lossy dielectric functions as a power sink, the higher order Bloch harmonic components arising from the structural periodicity are suppressed, and the mode spectrum of the lossy periodic system degenerates into that of an empty waveguide. This alleviates the potential danger of spurious oscillations induced by the higher order harmonic components, making the periodic lossy DL waveguide promising in a high-power millimeter-wave gyro-TWT. View full abstract»

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  • Information Processing With Pure Spin Currents in Silicon: Spin Injection, Extraction, Manipulation, and Detection

    Page(s): 2343 - 2347
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB) |  | HTML iconHTML  

    We demonstrate that information can be transmitted and processed with pure spin currents in silicon. Fe/Al2O3 tunnel barrier contacts are used to produce significant electron spin polarization in the silicon, generating a spin current which flows outside of the charge current path. The spin orientation of this pure spin current is controlled in one of three ways: 1) by switching the magnetization of the Fe contact; 2) by changing the polarity of the bias on the Fe/Al2O3 "injector" contact, which enables the generation of either majority or minority spin populations in the Si, providing a way to electrically manipulate the injected spin orientation without changing the magnetization of the contact itself; and 3) by inducing spin precession through the application of a small perpendicular magnetic field. Spin polarization by electrical extraction is as effective as that achieved by the more common electrical spin injection. The output characteristics of a planar silicon three-terminal device are very similar to those of nonvolatile giant magnetoresistance metal spin-valve structures. View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology