# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 30

Publication Year: 2009, Page(s):C1 - C4
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2009, Page(s): C2
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• ### Compact Modeling of the Temperature Dependence of Parasitic Resistances in SiGe HBTs Down to 30 K

Publication Year: 2009, Page(s):2169 - 2177
Cited by:  Papers (6)
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In this paper, we investigate the physics and modeling of temperature dependence of various parasitic resistances in SiGe heterojunction bipolar transistors down to 30 K. Carrier freezeout is shown to be the dominant contributor to increased resistances at cryogenic temperatures for lightly-doped and moderately-doped regions, whereas the temperature dependence of the mobility is the dominant contr... View full abstract»

• ### Effects of Self-Heating on Performance Degradation in AlGaN/GaN-Based Devices

Publication Year: 2009, Page(s):2178 - 2185
Cited by:  Papers (22)
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A self-consistent electrothermal transport model that couples electrical and thermal transport equations is established and applied to AlGaN/GaN device structures grown on the following three different substrate materials: 1) SiC; 2) Si; and 3) sapphire. Both the resultant I-V characteristics and surface temperatures are compared to experimental I -V measurements... View full abstract»

• ### Three-Dimensional Real-Space Simulation of Surface Roughness in Silicon Nanowire FETs

Publication Year: 2009, Page(s):2186 - 2192
Cited by:  Papers (31)
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We address the transport properties of narrow gate-all-around silicon nanowires in the presence of surface-roughness (SR) scattering at the Si/SiO2 interface, considering nanowire transistors with a cross section of 3 times 3 nm2 and gate length of 15 nm. We present transfer characteristics and effective-mobility calculations based on a full 3-D real-space self-consistent Poi... View full abstract»

• ### Band-to-Band Tunneling Ballistic Nanowire FET: Circuit-Compatible Device Modeling and Design of Ultra-Low-Power Digital Circuits and Memories

Publication Year: 2009, Page(s):2193 - 2201
Cited by:  Papers (25)
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Band-to-band tunneling (BTBT) nanowire FETs have been studied as a possible successor to CMOS FETs. In the literature, it has already been shown that a 1-D p+-i- n+-type semiconductor nanowire governed by a BTBT transport mechanism offers a subthreshold swing lower than the conventional limit of 60 mV/dec while maintaining a reasonable on-state performance. The concept of BTB... View full abstract»

• ### High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

Publication Year: 2009, Page(s):2202 - 2214
Cited by:  Papers (98)
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This paper presents a rigorous investigation of high-frequency effects in carbon nanotube (CNT) interconnects and their implications for the design and performance analysis of high-quality on-chip inductors. A frequency-dependent impedance extraction method is developed for both single-walled CNT (SWCNT) and multiwalled CNT (MWCNT) bundle interconnects. The method is subsequently verified by compa... View full abstract»

• ### The Quantum and Classical Capacitance Limits of InSb and InAs Nanowire FETs

Publication Year: 2009, Page(s):2215 - 2223
Cited by:  Papers (18)
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A comparison of nanowire FETs (NWFETs) of identical geometries but operating in two different regimes, namely, the quantum capacitance (QC) and classical capacitance (CC) regimes, is presented. n-type InSb and InAs NWFETs up to ~50 nm in diameter operate in the QC limit (QCL), and the corresponding p-type NWFETs operate in the CC limit. Drive currents at a fixed gate overdrive for the n- and p-typ... View full abstract»

• ### Implementation of Tunneling Phenomena in a CNTFET Compact Model

Publication Year: 2009, Page(s):2224 - 2231
Cited by:  Papers (16)
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This paper presents the implementation of band-to-band tunneling (BTBT) mechanisms into the compact model of a conventional carbon nanotube transistor FET featuring a MOSFET-like operation. Appropriate equations enable the calculation of the BTBT current as well as the charge pileup in the channel. To ensure the model accuracy and validate the equation set, the compact model simulation results are... View full abstract»

• ### Compact Model of Carbon Nanotube Transistor and Interconnect

Publication Year: 2009, Page(s):2232 - 2242
Cited by:  Papers (11)
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A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both I-V and C-V characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, a... View full abstract»

• ### Experimental Approach and Evaluation on Dynamic Reliability of PBGA Assembly

Publication Year: 2009, Page(s):2243 - 2249
Cited by:  Papers (21)
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The aim of this paper is to provide a systematic method to perform experimental test and theoretical evaluation on fatigue characteristics of plastic-ball-grid-array (PBGA) assembly under random vibration. A specified PBGA assembly which contains different structural and material parameters was manufactured. The fatigue characteristics of PBGA assembly under random vibration were tested. Manson-Co... View full abstract»

• ### Analytical and Finite-Element Modeling of a Cross Kelvin Resistor Test Structure for Low Specific Contact Resistivity

Publication Year: 2009, Page(s):2250 - 2254
Cited by:  Papers (9)
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Various test structures have been employed to determine the specific contact resistivity (rhoc) of ohmic contacts, and cross Kelvin resistor (CKR) test structures are most suitable for estimating low rhoc values. The value determined by CKRs includes error due to parasitic resistances that have been difficult to account for when rhoc is low (< 10-7 Omega ldr cm View full abstract»

• ### Analysis of Threshold Voltage Distribution Due to Random Dopants: A 100 000-Sample 3-D Simulation Study

Publication Year: 2009, Page(s):2255 - 2263
Cited by:  Papers (40)
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Using the Glasgow ldquoatomisticrdquo simulator, we have performed 3D statistical simulations of random-dopant-induced threshold voltage variation in state-of-the-art 35- and 13-nm bulk MOSFETs consisting of statistical samples of 105 or more microscopically different transistors. Simulation on such an unprecedented scale has been enabled by grid technology, which allows the distributio... View full abstract»

• ### Strained-$hbox{Si}_{1 - x}hbox{Ge}_{x}/hbox{Si}$ Band-to-Band Tunneling Transistors: Impact of Tunnel-Junction Germanium Composition and Doping Concentration on Switching Behavior

Publication Year: 2009, Page(s):2264 - 2269
Cited by:  Papers (52)
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Strained pseudomorphic Si/Si1-xGex/Si gate-controlled band-to-band tunneling (BTBT) devices have been analyzed with varying Ge composition up to 57% and p+ tunnel-junction (source) doping concentration in the 1019-1020 cm-3 range. Measurements show the impact of these parameters on the transfer and output characteristics. Measurements are comp... View full abstract»

• ### Undoped-Body Extremely Thin SOI MOSFETs With Back Gates

Publication Year: 2009, Page(s):2270 - 2276
Cited by:  Papers (48)  |  Patents (4)
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We present a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates. We show that short channel control improves with the application of back bias via a decrease in the electrostatic scaling length as the subthreshold charges move toward the front gate. We demonstrate that, even for undoped ETSOI devices ... View full abstract»

• ### Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $hbox{HfSiO}_{x}/hbox{TiSiN}$ Gate Stacks

Publication Year: 2009, Page(s):2277 - 2284
Cited by:  Papers (4)
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The short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current e... View full abstract»

• ### On the Experimental Determination of Channel Backscattering Characteristics—Limitation and Application for the Process Monitoring Purpose

Publication Year: 2009, Page(s):2285 - 2290
Cited by:  Papers (3)
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This paper reports a generalized temperature-dependent channel backscattering extraction method that can self-consistently determine the temperature sensitivity of the low-field mobility and the critical length in nanoscale MOSFETs. Through comparing the gate voltage and temperature dependence, we have shown that assuming constant temperature sensitivity of the low-field mobility and the critical ... View full abstract»

• ### Modeling and Analysis of Parasitic Resistance in Double-Gate FinFETs

Publication Year: 2009, Page(s):2291 - 2296
Cited by:  Papers (22)  |  Patents (1)
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A comprehensive model is presented to analyze the three-dimensional (3-D) source-drain (S/D) resistance of undoped double-gated FinFETs of wide and narrow S/D width. The model incorporates the contribution of spreading, sheet, and contact resistances. The spreading resistance is modeled using a standard two-dimensional (2-D) model generalized to 3-D. The contact resistance is modeled by generalizi... View full abstract»

• ### Analytic Model for Undoped Symmetric Double-Gate MOSFETs With Small Gate-Oxide-Thickness Asymmetry

Publication Year: 2009, Page(s):2297 - 2301
Cited by:  Papers (2)
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In this paper, an analytic model for undoped symmetric double-gate MOSFETs with small gate-oxide-thickness asymmetry is presented by virtue of a perturbation approach. Various effects on the MOSFET performance caused by small asymmetric departure from the nominal gate oxide thickness due to process variations and uncertainties are studied. This analytic solution can be used in compact models for I... View full abstract»

• ### Autonomous Refresh of Floating-Body Cell due to Current Anomaly of Impact Ionization

Publication Year: 2009, Page(s):2302 - 2311
Cited by:  Papers (4)  |  Patents (22)
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Physics of autonomous refresh is presented, which explains the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC). Input current to the floating body and output current from the body balance to generate an unstable stationary state that is accompanied by two stable stationary ones. The current anomaly of impact ionization is essential for the instability ... View full abstract»

• ### Self-Consistent SchrÖdinger–Poisson Simulations on Capacitance–Voltage Characteristics of Silicon Nanowire Gate-All-Around MOS Devices With Experimental Comparisons

Publication Year: 2009, Page(s):2312 - 2318
Cited by:  Papers (7)
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We simulate room temperature capacitance-voltage characteristics of silicon (Si) nanowire gate-all-around MOS structures with radius les 10 nm using a self-consistent Schrodinger- Poisson solver in cylindrical coordinates with full treatment of the transverse quantum confinement. In this paper, we compare our simulation results with the latest capacitance measurements on single Si nanowire pMOS an... View full abstract»

• ### Effects of the Localization of the Charge in Nanocrystal Memory Cells

Publication Year: 2009, Page(s):2319 - 2326
Cited by:  Papers (2)
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In this paper, we present a peculiar characteristic of nanocrystal (NC) memory (NCM) cells: The programming (P) windows measured in linear and subthreshold regions are different. A floating-gate flash memory cell with a similar structure does not show the same behavior, and the P window (PW) is independent of the current level of the extrapolation, as expected. By performing 2-D TCAD simulations, ... View full abstract»

• ### Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator

Publication Year: 2009, Page(s):2327 - 2334
Cited by:  Papers (49)
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Based on the continuity theorem of electric displacement including interface charges, the enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices is proposed. The following three approaches for enhancing the dielectric layer electric field EI to increase the vertical breakdown voltage of a device VB,V are presented: 1) using a thin silicon ... View full abstract»

• ### A Lossy Dielectric-Ring Loaded Waveguide With Suppressed Periodicity for Gyro-TWTs Applications

Publication Year: 2009, Page(s):2335 - 2342
Cited by:  Papers (14)
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A dielectric-loaded (DL) waveguide is an attractive possibility for interaction circuits with high-power sources in the millimeter-wave regime down to tenths of millimeters, particularly for gyrotron-traveling-wave-tube amplifiers (gyro-TWTs). We present results on a systematic investigation of the influence of the periodically loaded lossy dielectric on the propagation characteristics of the oper... View full abstract»

• ### Information Processing With Pure Spin Currents in Silicon: Spin Injection, Extraction, Manipulation, and Detection

Publication Year: 2009, Page(s):2343 - 2347
Cited by:  Papers (28)
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We demonstrate that information can be transmitted and processed with pure spin currents in silicon. Fe/Al2O3 tunnel barrier contacts are used to produce significant electron spin polarization in the silicon, generating a spin current which flows outside of the charge current path. The spin orientation of this pure spin current is controlled in one of three ways: 1) by switch... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy