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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 10 • Date Oct. 2009

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  • Table of contents

    Publication Year: 2009 , Page(s): C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2009 , Page(s): C2
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  • Elastic Circuits

    Publication Year: 2009 , Page(s): 1437 - 1455
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1389 KB) |  | HTML iconHTML  

    Elasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with synchronous design. Elasticity can be implemented both synchronously and asynchronously, although it was traditionally more often associated with asynchronous circuits. This paper shows that synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques. Thus, choices between synchronous and asynchronous implementations are localized and deferred until late in the design process. View full abstract»

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  • Simulation of Mutually Coupled Oscillators Using Nonlinear Phase Macromodels

    Publication Year: 2009 , Page(s): 1456 - 1466
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (555 KB) |  | HTML iconHTML  

    Design of integrated RF circuits requires detailed insight in the behavior of the used components. Unintended coupling and perturbation effects need to be accounted for before production, but full simulation of these effects can be expensive or infeasible. In this paper, we present a method to build nonlinear phase macromodels of voltage-controlled oscillators. These models can be used to accurately predict the behavior of individual and mutually coupled oscillators under perturbation at a lower cost than full circuit simulations. The approach is illustrated by numerical experiments with realistic designs. View full abstract»

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  • Stable Reduced Models for Nonlinear Descriptor Systems Through Piecewise-Linear Approximation and Projection

    Publication Year: 2009 , Page(s): 1467 - 1480
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1070 KB) |  | HTML iconHTML  

    This paper presents theoretical and practical results concerning the stability of piecewise-linear (PWL) reduced models for the purposes of analog macromodeling. Results include proofs of input-output (I/O) stability for PWL approximations to certain classes of nonlinear descriptor systems, along with projection techniques that are guaranteed to preserve I/O stability in reduced-order PWL models. We also derive a new PWL formulation and introduce a new nonlinear projection, allowing us to extend our stability results to a broader class of nonlinear systems described by models containing nonlinear descriptor functions. Lastly, we present algorithms to compute efficiently the required stabilizing nonlinear left-projection matrix operators. View full abstract»

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  • Closed-Form Delay and Crosstalk Models for RLC On-Chip Interconnects Using a Matrix Rational Approximation

    Publication Year: 2009 , Page(s): 1481 - 1492
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1314 KB) |  | HTML iconHTML  

    In this paper, a closed-form matrix rational-approximation algorithm is proposed to efficiently model the delay and crosstalk noise of coupled RLC on-chip interconnects. A key feature of the proposed algorithm is that, for any rational order, the approximation is obtained analytically in terms of predetermined coefficients and the per-unit-length parameters. As a result, the proposed method is not limited to fixed number of poles and provides a mechanism to increase the accuracy for cases when inductive effects are significant, the length of the line increases, or when the rise time of the signal becomes sharper. An error criterion is provided to select the order of approximation. The algorithm is tested for various single- and coupled-interconnect scenarios. The 50% delay and overshoot results match that of SPICE with less than 2% average error. The crosstalk results also accurately match those of SPICE with less than 4% average error. View full abstract»

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  • HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection

    Publication Year: 2009 , Page(s): 1493 - 1502
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1057 KB) |  | HTML iconHTML  

    Hardware intellectual-property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs from IP piracy. This paper proposes a novel design methodology for hardware IP protection using netlist-level obfuscation. The proposed methodology can be integrated in the SoC design and manufacturing flow to simultaneously obfuscate and authenticate the design. Simulation results for a set of ISCAS-89 benchmark circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint. View full abstract»

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  • Utilizing Predictors for Efficient Thermal Management in Multiprocessor SoCs

    Publication Year: 2009 , Page(s): 1503 - 1516
    Cited by:  Papers (27)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1334 KB) |  | HTML iconHTML  

    Conventional thermal management techniques are reactive, as they take action after temperature reaches a threshold. Such approaches do not always minimize and balance the temperature, and they control temperature at a noticeable performance cost. This paper investigates how to use predictors for forecasting temperature and workload dynamics, and proposes proactive thermal management techniques for multiprocessor system-on-chips. The predictors we study include autoregressive moving average modeling and lookup tables. We evaluate several reactive and predictive techniques on an UltraSPARC T1 processor and an architecture-level simulator. Proactive methods achieve significantly better thermal profiles and performance in comparison to reactive policies. View full abstract»

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  • Electronic System-Level Synthesis Methodologies

    Publication Year: 2009 , Page(s): 1517 - 1530
    Cited by:  Papers (30)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (913 KB) |  | HTML iconHTML  

    With ever-increasing system complexities, all major semiconductor roadmaps have identified the need for moving to higher levels of abstraction in order to increase productivity in electronic system design. Most recently, many approaches and tools that claim to realize and support a design process at the so-called electronic system level (ESL) have emerged. However, faced with the vast complexity challenges, in most cases at best, only partial solutions are available. In this paper, we develop and propose a novel classification for ESL synthesis tools, and we will present six different academic approaches in this context. Based on these observations, we can identify such common principles and needs as they are leading toward and are ultimately required for a true ESL synthesis solution, covering the whole design process from specification to implementation for complete systems across hardware and software boundaries. View full abstract»

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  • Maximum-Utility Scheduling of Operation Modes With Probabilistic Task Execution Times Under Energy Constraints

    Publication Year: 2009 , Page(s): 1531 - 1544
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (731 KB) |  | HTML iconHTML  

    We propose a novel scheduling scheme that determines the instant operation modes of multiple tasks. The tasks have probabilistic execution times and are executed on discrete operation modes providing different utilities with different energy consumptions. We first design an optimal offline scheduling scheme that stochastically maximizes the cumulative utility of the tasks under energy constraints, at the cost of heavy computational overhead. Next, the optimal offline scheme is modified to an approximate online scheduling scheme. The online scheme has little runtime overhead and yields almost the maximum utility, with an energy budget that is given at runtime. The difference between the maximum utility and the output utility of the online scheme is bounded by a controllable input value. Extensive evaluation shows that the output utility of the online scheme approaches the maximum utility in most cases, and is much higher than that of existing methods by up to 50% of the largest utility difference among available operation modes. View full abstract»

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  • Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)

    Publication Year: 2009 , Page(s): 1545 - 1558
    Cited by:  Papers (18)  |  Patents (44)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (737 KB) |  | HTML iconHTML  

    Instruction Footprint Recording and Analysis (IFRA) overcomes challenges associated with an expensive step in post-silicon validation of processors-pinpointing the bug location and the instruction sequence that exposes the bug from a system failure. On-chip recorders collect instruction footprints (information about flows of instructions and what the instructions did as they passed through various design blocks) during the normal operation of the processor in a post-silicon system validation setup. Upon system failure, the recorded information is scanned out and analyzed offline for bug localization. Special self-consistency-based program analysis techniques, together with the test program binary of the application executed during post-silicon validation, are used for this purpose. Major benefits of using IFRA over traditional techniques for post-silicon bug localization are as follows: 1) it does not require full system-level reproduction of bugs, and 2) it does not require full system-level simulation. Simulation results on a complex superscalar processor demonstrate that IFRA is effective in accurately localizing electrical bugs with very little impact on overall chip area. View full abstract»

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  • Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints

    Publication Year: 2009 , Page(s): 1559 - 1572
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2185 KB) |  | HTML iconHTML  

    This paper describes a fast and accurate technique to predict the steady-state throughput and the corresponding power consumption of a homogeneous multicore processor for a given benchmark workload while accounting for speed reduction due to thermal constraints. The expressions contain several parameters of interest to a system designer, like the static and dynamic-power consumptions (for hottest block and for full chip), the vertical thermal resistance of the hottest block, the leakage sensitivity to temperature, the chip threshold temperature, the ambient temperature, etc. Their computational complexity is independent of the number of cores. These are incorporated in a system-level multicore power/thermal simulator that uses the PTScalar power model and the Hotspot thermal model. The analytical throughput and power predictions were within 1.7% of that predicted by the system-level simulator. However, the analytical technique takes less than 0.2 s for a given set of design parameters, making it well suited for early design-space exploration. In contrast, the numerical technique takes anywhere from a minute (for 4 cores) up to a few hours (for 25 cores). View full abstract»

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  • A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects

    Publication Year: 2009 , Page(s): 1573 - 1582
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1666 KB) |  | HTML iconHTML  

    Interconnect defects such as weak resistive opens, shorts, and bridges increase the path delay affected by a pattern during manufacturing test but are not significant enough to cause a failure at functional frequency. In this paper, a new faster-than-at-speed method is presented for delay test pattern application to screen small delay defects. Given a test pattern set, the technique groups the patterns into multiple subsets with close path delay distribution and determines an optimal test frequency considering both positive slack and performance degradation due to IR-drop effects. Since, the technique does not increase the test frequency to an extent that any paths exercised at the rated functional frequency may fail, it avoids any scan flip-flop masking. As most semiconductor companies currently deploy compression technologies to reduce test costs, scan-cell masking is highly undesirable for pattern modification as it would imply pattern count increase and might result in pattern regeneration. Therefore, our solution is more practical as the test engineer can run the same pattern set without any changes to the test flow other than the at-speed test frequency. View full abstract»

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  • High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability

    Publication Year: 2009 , Page(s): 1583 - 1596
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (907 KB) |  | HTML iconHTML  

    A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with hierarchical test-pattern generation for embedded modules, guarantees a 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay-fault coverage is usually attributed to the fact that a two-pattern test for delay testing cannot be delivered to modules under test in two consecutive cycles. To solve the problem, we propose an HLTS method that ensures that valid test pairs can be sent to each module through synthesized circuit hierarchy. Experimental results show that this method achieves 100% fault coverage for transition faults in modules; in contrast, the fault coverage in circuits synthesized by a left-edge-algorithm-based allocation algorithm is rather poor. The area overhead due to this method ranges from 1% to 10% for 16-b datapath circuits. On the other hand, hierarchical test patterns cannot provide good delay-fault coverage for faults in interconnection structure and registers. The reason is that some control sequences required for delay-fault detection cannot be provided by the controller. We propose two design-for-testability insertion methods to deal with this problem. Experimental results show that, on the average, at least 11% higher delay-fault coverage is achieved by these methods. View full abstract»

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  • Automated Design Debugging With Abstraction and Refinement

    Publication Year: 2009 , Page(s): 1597 - 1608
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (342 KB) |  | HTML iconHTML  

    Design debugging is one of the major remaining manual processes in the semiconductor design cycle. Despite recent advances in the area of automated design debugging, more effort is required to cope with the size and complexity of today's designs. This paper introduces an abstraction and refinement methodology to enable current debuggers to operate on designs that are orders of magnitude larger than otherwise possible. Two abstraction techniques are developed with the goals of improving debugger performance for different circuit structures: State abstraction is aimed at reducing the problem size for circuits consisting purely of primitive gates, while function abstraction focuses on designs that also contain modular and hierarchical information. In both methods, after an initial abstracted model is created, the problem can be solved by an existing automated debugger. If an error site is abstracted, refinement is necessary to reintroduce some of the abstracted components back into the design. This paper also presents the underlying theory to guarantee correctness and completeness of a debugging tool that operates using the proposed methodology. Empirical results demonstrate improvements in run time and memory capacity of two orders of magnitude over a state-of-the-art debugger on a wide range of benchmark and industrial designs. View full abstract»

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2009 , Page(s): 1609
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    Publication Year: 2009 , Page(s): 1610
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    Publication Year: 2009 , Page(s): 1611
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    Publication Year: 2009 , Page(s): 1612
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2009 , Page(s): C3
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu