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Electron Devices, IEEE Transactions on

Issue 4 • Date April 1993

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Displaying Results 1 - 24 of 24
  • Comments on Transient analysis of stored charge in neutral base region [with reply]

    Page(s): 833 - 835
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    The commenter addresses questions raised in the above-titled paper by K. Suzuki et al. (ibid., vol.39, p.1164-9, May 1992) concerning the validity of bipolar transistor models using the partitioned-charge (PC) approach for transient simulations. Suzuki et al. assert that the concept of charge partitioning applies only to discharge transients and thus the charge-partition ratio depends on the sign of the emitter-base voltage gradient, which, if true, would greatly reduce the utility of PC-based models. The commenter shows that this is not the case and that their conclusion is due only to a misinterpretation of the PC model. The authors reply.<> View full abstract»

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  • Analytic accounting for carrier velocity overshoot in advanced BJT's for circuit simulation

    Page(s): 789 - 795
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    An analytic model for electron velocity overshoot in advanced silicon-based bipolar junction transistors (BJTs) is presented. The model, which characterizes an effective saturated drift velocity in the collector space-charge regions, is intended for circuit simulation and has been implemented in MMSPICE. The model is based on a nonlocal augmented drift-velocity formalism that involves a length coefficient derived from Monte Carlo simulations. A phenomenological representation of the associated velocity relaxation is defined to be consistent with the overshoot analysis. Demonstrative MMSPICE device and circuit simulations show that effects of velocity overshoot in contemporary silicon BJTs produce only small performance enhancements, but can be exploited to optimize design tradeoffs in scaled technologies View full abstract»

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  • Resolving degradation mechanisms in ultra-high performance N-p-n heterojunction bipolar transistors

    Page(s): 692 - 697
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    The conduction band barrier caused by base dopant outdiffusion is investigated for MBE-grown AlxGa1-xAs/GaAs N-p-n linearly graded heterojunction bipolar transistors (HBTs). The change of the B-E heterojunction conduction band barrier can be directly revealed by a novel technique based on the diffusion-thermionic emission current model. This is accomplished by measuring the inverted collector current ratio at two different heterojunction reverse biases. In addition, this ratio is found to correlate with an anomalous base current component measured at low temperature. The heterojunction potential barrier and the anomalous base current component are attributed to beryllium redistribution during MBE growth and forward current stress. This suggests that the diffusion and incorporation of beryllium dictate V BE uniformity and long-term reliability of HBTs View full abstract»

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  • Secondary emission formulas

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB)  

    A minor revision is made to the author's `A New Formula for Secondary Emission Yield' (ibid., vol.36, no.9, p.1963-7, September 1989) based on the work of A. Shih and C. Hor reported elsewhere in this issue (ibid. vol.40, no.4, p.824-9, Apr. 1993) View full abstract»

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  • Sensitive optical gating of reverse-biased AlGaAs/GaAs optothyristors for pulsed power switching applications

    Page(s): 817 - 823
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    A heterojunction-based optothyristor has been fabricated and tested with biasing field intensity up to 34 kV/cm for pulsed power applications. The reverse-biased optothyristor can even be triggered by a light-emitting diode (LED) of a few microwatts power, and more than 500 times reduction in the required LED power for triggering has been observed when compared to bulk photoconductive switches. The optothyristor, however, does not turn on under similar triggering conditions if bias polarity is changed. The sensitive optical gating of the reverse-biased optothyristor is explained. The turn-on delay time under reverse bias has been found to be inversely proportional to the square root of the LED power. The possibility of improving the switching efficiency by superimposing the laser pulse on a constant lower level background illumination has been demonstrated View full abstract»

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  • Modeling and characterization of SIPOS emitter and quasi-SIS emitter bipolar transistors

    Page(s): 796 - 803
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    SIPOS (semi-insulating polycrystalline Si) emitter bipolar transistors have been fabricated with a common-emitter current gain of 8000 and a figure of merit (gain divided by intrinsic base sheet resistance) of 200 (kΩ/sq)-1. The high gain is attributed to a relatively low interface recombination velocity of the emitter contact, as measured by photo-induced microwave reflectometry. The cutoff frequency is measured to be 250 MHz, the low value attributed to a large emitter contact resistance of the SIPOS emitter. The authors suggest that a new figure of merit-transconductance divided by emitter resistance-should be considered for the comparison of the high-frequency performances of high emitter efficiency bipolar transistors. A quasi-SIS semiconductor-insulator-semiconductor emitter bipolar with a poly-Si emitter and undoped SIPOS as an interfacial layer was also fabricated. By incorporating a field-enhancement factor in the SIPOS, the behavior of this transistor is successfully explained by a SIS emitter model. The ideality factor ratio in the Gummel plot is attributed to the different barrier heights of electrons and holes at the SiO2/n-Si interface View full abstract»

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  • An analytical open-failure lifetime model for stress-induced voiding in aluminum lines

    Page(s): 782 - 788
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    An analytical model is derived for determining the time before which LSI aluminum (Al) lines with a bamboo-grain structure undergo open failures caused by stress-induced voiding. Derivations are based on the following assumptions: that the driving force for void growth is relaxation of Al-line tensile stress, that the mass transport rate is proportional to the nth power of Al-line stress, and that the void will maintain its prism shape throughout its growth. The critical minimum initial tensile stress value for producing open failure is calculated, as are the respective dependencies of lifetime on void tip angle, temperature, line dimensions, and line tensile stress. By adjusting the values of certain parameters within the model, it is possible to derive temperature, line-dimension, and tensile-stress dependencies that fall within the range of experimentally obtained results View full abstract»

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  • Numerical simulation of sidegating effect in GaAs MESFET's

    Page(s): 698 - 704
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    Two-dimensional simulation of the sidegating effect in GaAs MESFETs has been performed. The result confirms that Schottky contacts on a semi-insulating substrate cause serious high substrate leakage current and drain current reduction in GaAs MESFETs. The threshold behavior in the sidegating effect is found to correlate with the conduction behavior of the Schottky-i-n (sidegate) structure when the sidegate is negatively biased. Shielding and enhancement of the sidegating effect by the Schottky contacts have also been studied, and the results agree with the experimental findings. Besides, the presence of hole traps in the semi-insulating substrate is found to be essential to the sidegating effect View full abstract»

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  • Evidence of different conduction mechanisms in accumulation-mode p-channel SOI MOSFET's at room and liquid-helium temperatures

    Page(s): 727 - 732
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    The threshold voltage for the three different conduction components of an accumulation-mode PMOS SOI were experimentally extracted at room and liquid-helium temperatures. A deep-depletion transient effect was observed to play an important role when one of the interfaces was in inversion, even at room temperature. An intuitive physical interpretation is given for the suppression of some current components at liquid-helium temperatures. In addition, a simple model for calculating the silicon-film thickness and the doping level is presented View full abstract»

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  • Transit-time model for short-channel MOSFET's

    Page(s): 830 - 832
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    A new analytical transit-time model for submicrometer MOS devices has been developed. The model is based on a modified SPICE level-three MOSFET DC model, and it allows the use of a physical value for the charge carrier saturation velocity. This is essential for accurate transit-time modeling. Both DC and transit-time models show good agreement with the results obtained from more complicated two-dimensional numerical simulations View full abstract»

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  • Secondary emission properties as a function of the electron incidence angle

    Page(s): 824 - 829
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    Computer codes being developed to improve the understanding of crossed-field amplifier (CFA) performance require a more complete and reliable database of the secondary electron emission properties of the electrode materials than exists in the literature. The authors describe an experimental method and present results of secondary emission yield measurements on molybdenum surfaces, both clean and gas-exposed. The surface cleanliness was monitored by Auger electron spectroscopy (AES), and all measurements were made under ultrahigh-vacuum conditions (better than 1×10-10 torr). The results differ from the existing data for which the surface cleanliness was not determined. The secondary electron emission yields were measured as a function of the primary electron energy and also of the angle of incidence. The results were fitted with the analytical expressions of J.R.M. Vaughan (1989), with good overall agreement if Vaughan's formulas are slightly modified View full abstract»

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  • Drain-induced barrier lowering in buried-channel MOSFET's

    Page(s): 741 - 749
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    In the literature, it is unclear whether or not buried-channel (BC) MOSFETs are less resistant to drain-induced barrier lowering than surface-channel MOSFETs. The authors clarify this confusion and experimentally demonstrate the relationship between the threshold voltage and channel length reduction for normally-on (inverting) BC-MOSFETs. The results are compared with similar measurements on surface-channel MOSFETs. It is shown that BC-MOSFETs are more prone to drain-induced barrier lowering than surface-channel MOSFETs. A simple analytic model is derived for the subthreshold current in small-geometry BC-MOSFETs. The model shows good agreement with experimental measurements and with subthreshold currents obtained using a two-dimensional numerical simulator View full abstract»

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  • Transversal and longitudinal noise and their coherence in MOST

    Page(s): 804 - 810
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    The thermal and 1/f noise have been studied in MOSTs with side contacts along the channel. In difference biasing conditions, the distribution of the transversal noise in the channel has been explained in terms of the local values, including surface concentration, noise parameter, and mobility. Below saturation, the calculations are in good agreement with the observed experimental data. At saturation, the 1/f noise source strength seems to be nonuniform, along the channel, and the simple model deviates from experimental results. Possible reasons for this are discussed. The observed transversal noise and the coherence of longitudinal noise indicate that 1/f noise is uniformly generated through the channel in the ohmic region. However, there is no proof of the hypothesis that temperature fluctuation is the origin of the 1/f noise. A simple expression is derived to estimate the ratio of transversal to longitudinal noise in terms of channel geometric parameters. For MOSTs biased in the ohmic region at high gate voltage there is good agreement between experimental and calculated results View full abstract»

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  • Investigation of alternative window materials for GaAs solar cells

    Page(s): 705 - 711
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    The optimum window material for surface passivation of GaAs solar cells is investigated using theoretical analysis of optical losses due to window bandgap energy and thickness. A simplified expression is developed to calculate the effective surface recombination velocity in terms of lattice mismatch between the window layer and GaAs, which suggests using a window material with and indirect bandgap energy greater than 2.0 eV, a thickness of less than 0.05 μm, and a lattice mismatch of less than 0.05%. Experimental GaAs solar cells were fabricated and quantum efficiency measurements were made using no window (bare GaAs), Al0.7Ga0.3As, Na2S, and ZnSe/Na2S windows. The Al0.7Ga0.3As and Na2S windows are shown to passivate the GaAs surface and reduce the surface recombination velocity to less than 105 cm/s, while the ZnSe encapsulating layer was used to permanently maintain the temporary surface passivation effects from Na2S View full abstract»

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  • An analytical back-gate bias effect model for ultrathin SOI CMOS devices

    Page(s): 755 - 765
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    An analytical back-gate bias effect model for ultrathin SOI CMOS devices is presented. As verified by PISCES results, the analytical SOI CMOS back-gate bias effect model provides a much better accuracy in the integral potential distribution and the threshold voltage as the back-gate bias is changed View full abstract»

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  • An a-Si:H/a-Si,Ge:H bulk barrier phototransistor with a-SiC:H barrier enhancement layer for high-gain IR optical detector

    Page(s): 721 - 726
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    The design and fabrication of a high-gain amorphous silicon/amorphous silicon germanium (a-Si:H/a-Si,Ge:H) bulk barrier phototransistor for infrared light detection applications are reported. The a-Si,Ge:H material featured a lower energy gap and is suitable for the absorption of longer wave light, but it also leads to a low breakdown voltage and high dark current. An additional a-SiC:H thin-film layer was used at the collector/base interface in the conventional amorphous bulk barrier phototransistor to enhance the function of the bulk barrier and obtain high optical gain View full abstract»

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  • Analysis of heterojunction bipolar transistor/resonant tunneling diode logic for low-power and high-speed digital applications

    Page(s): 685 - 691
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    A high-speed digital logic family based on heterojunction bipolar transistors (HBTs) and resonant tunneling diodes (RTDs) is proposed. The negative differential resistance of RTDs is used to significantly decrease the static power dissipation. SPICE simulations indicate that propagation delay time below 150 ps at 0.09-mW static power per gate should be obtainable View full abstract»

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  • A closed-form analytical forward transit time model considering specific models for bandgap-narrowing effects and concentration-dependent diffusion coefficients for BJT devices operating at 77 K

    Page(s): 766 - 772
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    The authors report a closed-form analytical low-temperature forward transit time model considering bandgap-narrowing effects and concentration-dependent diffusion coefficients based on the entire shape of the emitter and base doping profiles for bipolar junction transistor (BJT) devices operating at 77 K. As verified by the PISCES simulation results, the new closed-form analytical model provides a better low-temperature forward transit time model compared to the model in which bandgap-narrowing effects and concentration-dependent diffusion coefficients are not considered View full abstract»

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  • Absence of quantum 1/f noise in the photoelectric current of junction of MIS photodetectors

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (88 KB)  

    Quantum 1/f noise is given by a simple engineering formula. It affects photodetectors through mobility and recombination speed fluctuations. The former are also in the diffusion constant, and all affect the dark current. However, there is no quantum 1/f noise in the photogeneration of carriers, as is shown View full abstract»

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  • Avalanche breakdown and surface deep-level trap effects in GaAs MESFET's

    Page(s): 811 - 816
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    Time-dependent numerical simulations have been performed to investigate avalanche breakdown and surface deep-level trapping effects in GaAs MESFETs. The model is based on a combination of bipolar drift-diffusion transport, impact ionization, and a dynamic surface charging mechanism. A realistic trapping process is introduced into the surface trap model from which the spatial distribution of surface charge density is determined. The basic breakdown mechanisms, gate-bias-dependent breakdown voltages, and effects of surface charges are demonstrated. It is shown that the surface deep-level traps have a pronounced effect on the breakdown phenomenon View full abstract»

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  • Spread-vertical-capacitor cell (SVC) for high-density dRAM's

    Page(s): 750 - 754
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    An advanced three-dimensionally (3-D) stacked-capacitor cell, the spread-vertical-capacitor cell (SVC), was developed. SVC realized a storage capacitance (Cs) of 30 fF with a cell area of 1.8 μm2, a capacitor height of 0.37 μm, and an equivalent SiO2 film thickness of 7 nm for oxide-nitride-oxide (ONO). By extrapolating these results to 256-Mb DRAMs, a Cs of 24 fF is obtained with a cell area of 0.5 μm2, a capacitor height of 0.4 μm, and an equivalent SiO2 thickness of 5 nm, and these values satisfy the specifications for 256-Mb DRAMs. The low capacitor height of SVC makes possible a fabrication process using ArF excimer laser lithography View full abstract»

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  • A new I-V model for short gate-length MESFET's

    Page(s): 712 - 720
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    An I-V model for short gate-length MESFETs operated in the turn-on region is proposed, in which the two-dimensional potential distributions contributed by the depletion-layer charges under the gate and in the ungated region are separately obtained by conventional 1-D approximation and the Green's function solution technique. Moreover, the bias-dependent parasitic resistances due to the modulation of the depletion layer in the ungated region for non-self-alignment MESFETs are also taken into account in the developed I-V model. It is shown that good agreement is obtained between the I-V model and the results of 2-D numerical analysis. Moreover, comparisons between the proposed analytical model and the experimental data are made, and excellent agreement is obtained View full abstract»

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  • A critical examination of the assumptions underlying macroscopic transport equations for silicon devices

    Page(s): 733 - 740
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    Assumptions used to derive macroscopic transport equations for silicon devices are critically examined. The position- and momentum-dependent distribution function for a silicon n-i-n diode is obtained from a rigorous solution to the Boltzmann equation, and various macroscopic quantities, such as the electron temperature tensor, energy and heat fluxes, and mobility, are rigorously evaluated and compared with widely used approximations. The common approximation of the heat flux by Fourier's law is shown to differ substantially from the actual heat flux. The results also show that at a given energy, the mobility within a submicrometer device can be much different than that for electrons at the same energy in bulk silicon View full abstract»

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  • A coupled study by floating-gate and charge-pumping techniques of hot carrier-induced defects in submicrometer LDD n-MOSFET's

    Page(s): 773 - 781
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    The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from Vd/8 to Vd) by hot-hole and/or hot-electron injections, and their generation rates (10-9 and 10-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the Id-Vg degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I d-Vg degradation View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology